R
Rudy Lauwereins
Researcher at Katholieke Universiteit Leuven
Publications - 49
Citations - 3816
Rudy Lauwereins is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Field-programmable gate array & Artificial neural network. The author has an hindex of 24, co-authored 46 publications receiving 3652 citations. Previous affiliations of Rudy Lauwereins include IMEC.
Papers
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Book ChapterDOI
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
TL;DR: A novel architecture with tightly coupled very long instruction word (VLIW) processor and coarse-grained reconfigurable matrix is proposed, which has good performance and is very compiler-friendly.
Journal ArticleDOI
Cycle-static dataflow
TL;DR: The CSDF paradigm is an extension of synchronous dataflow that still allows for static scheduling and, thus, a very efficient implementation of an application and it is indicated that CSDF is essential for modelling prescheduled components, like application-specific integrated circuits.
Proceedings ArticleDOI
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling
TL;DR: A modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures and is a key part of theDRESC Dynamically Reconfigurable Embedded Systems Compiler.
Proceedings ArticleDOI
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
TL;DR: This paper presents a retargetable compiler for a family of coarse-grained reconfigurable architectures and presents experimental results, showing up to 28.7 instructions per cycle (IPC) over tested kernels.
Book ChapterDOI
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
Théodore Marescaux,Andrei Bartic,Diederik Verkest,Diederik Verkest,Serge Vernalde,Rudy Lauwereins,Rudy Lauwereins +6 more
TL;DR: This paper explains how separating communication from computation enables hardware multi-tasking and describes the implementation of a fixed communication-layer that decouples the computation elements, allowing them to be dynamically reconfigured.