This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in a good agreement and show that the proposed design has great potential for multichannel applications; the averaged DNL_(pk-pk) and INL_(pk-pk) are close to or even less than 0.05 LSB in multichannel designs.

/pdf/128-channel-high-linearity-resolution-adjustable-time-to-4ny186l3oz.pdf

128-channel high-linearity resolution- adjustable time-to-digital converters for LiDAR applications: software predictions and hardware implementations

The Stochastic Phase-Interpolation Time-to-Digital Converter (SPI-TDC) leverages redundancy to tolerate Process-Voltage-Temperature (PVT) variations. This article presents a comprehensive analysis of the linearity of the SPI-TDC and its error mechanisms, and proposes a linearization technique to reduce the redundancy requirement. Using deterministic and stochastic models, this article analyzes the effects of the unit delay, length of the delay-line, clock frequency, jitter, and mismatch on the linearity of the SPI-TDC, and prescribes a compact set of design equations to guide the designer. Based on the results of the analysis, the article proposes a robust solution using a Delay-Locked Loop (DLL) to linearize the SPI-TDC with reduced hardware and power overhead. This article also analyzes, for the first time, the loop dynamics of a DLL accounting for the delay of the delay-line. Measurements of an 8-bit, 60-MHz SPI-TDC validate the theories and demonstrate the effectiveness of the proposed solution across supply and temperature variations while using only $4\times $ redundancy.

Linearity Theory of Stochastic Phase-Interpolation Time-to-Digital Converter

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514 S/s prototype (ReDAC1) and on a 11-bit, 10.5 kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68 LSB (1.53 LSB) maximum INL, 1.54 LSB (1.0 LSB) maximum DNL, 76.4 dB (67.9 dB) THD, 79.7 dB (71.4 dB) SFDR and 71.3 dB (63.3 dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB).

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

This article proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf DN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf IN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> are close to or even less than 0.05 LSB in multichannel designs. 

/pdf/128-channel-high-linearity-resolution-adjustable-time-to-hr8lvk44.pdf

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

This paper presents a 20-channel coincidence counting unit (CCU) using a low-end field-programmable gate array (FPGA). The architecture of the CCU can be configured arbitrarily to measure from twofold to twentyfold coincidence counts thanks to a multifold controllable architecture, which can be easily manipulated by a graphical user interface (GUI) program. In addition, it provides up to 20 of each input signal count simultaneously. The experimental results show twentyfold coincidence counts with the resolution occurring in a less than 0.5 ns coincidence window. This CCU has appropriate characteristics for various quantum optics experiments using multi-photon qubits.

https://www.mdpi.com/2079-9292/10/5/569/pdf

Arbitrary configurable 20-channel coincidence counting unit for multi-qubit quantum experiment

An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely −0.157 to 0.137 LSB, −0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

A low flicker dimmable four-channel LED driver with precise current balancing is proposed in this paper. It is able to achieve highly linear dimming and low lighting flicker at the same time by utilizing a new matrix-style digital pulsewidth modulation (DPWM) along with LED string rotation. Only one LED string needs to be modulated to reduce the total LED current variation and switching loss. To avoid color shift and reduce the effect of subharmonic flicker, a fourth-order common centroid layout is applied to match the current-controlling MOSFETs for precise current balancing. Low-voltage and high-temperature protection circuits as well as a temperature-compensated relaxation oscillator are all integrated to complete the driver design and reduce the overall cost for practical applications. The chip is designed in a TSMC 0.25- $\mu \text{m}$ 1P3M 60-V high-voltage CMOS process with a chip size of $1.76\times1.37$ mm2. The current mismatch among LED strings is measured to be only ±0.28% along with four times reduction in lighting flicker.

Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching

A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as −1.470– 1.676 LSB for Stratix IV to demonstrate its excellent linearity.

https://ieeexplore.ieee.org/ielx7/6287639/6514899/09967976.pdf

Ruei-Ting Wang

Papers

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection