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Runsheng Wang

Bio: Runsheng Wang is an academic researcher from Peking University. The author has contributed to research in topics: Computer science & Circuit design. The author has an hindex of 23, co-authored 217 publications receiving 1940 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time, and the results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog and RF applications.
Abstract: In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

99 citations

Journal ArticleDOI
TL;DR: In this article, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET.
Abstract: In this paper, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET. It is found that the Vth shifts and subthreshold swing (SS) degradation induced by interface traps in TFET and MOSFET have the same trends, but the impacts on ION are different because of the novel conduction mechanism of TFETs when compared with MOSFETs. Moreover, nTFET is intrinsically more immune (or susceptible) to Vth shift induced by acceptor(or donor-) type interface traps than nMOSFET. Therefore, reducing the potential degradation induced by the interface traps can be achieved by optimizing the position of CNL. The results indicate that nTFET is more immune to the Vth shift than nMOSFET with CNL below a critical energy. In addition, the trap-induced SS degradation of TFET is severer than MOSFET in electrostatics. Moreover, it is found that the ION, Vth, and IOFF fluctuations in nMOSFET and nTFET are also dependent on the position of CNL. With CNL below the critical energy, the ION fluctuation and Vth fluctuation of nTFET are smaller than those of nMOSFET. The results are helpful for the interface optimization of TFETs.

94 citations

Journal ArticleDOI
TL;DR: In this article, low-frequency noise (LFN) in n-type silicon nanowire MOSFETs is investigated and the measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed.
Abstract: Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain-current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.

78 citations

Journal ArticleDOI
TL;DR: In this article, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach.
Abstract: As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.

67 citations

Journal ArticleDOI
TL;DR: It is shown that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation and by designing the device channels along the lower effective mass armchair direction.
Abstract: As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/μm at 300 K and 1.6 mA/μm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.

63 citations


Cited by
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Journal ArticleDOI
TL;DR: The tunnel field effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage as mentioned in this paper.
Abstract: The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $\mathrm{V}_{\rm DD}$ ). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at $\mathrm{L}_{\rm G}= 13$ nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional $\mathrm{V}_{\rm DD}$ . Also, P-TFET current-drive is between $1\times $ to $0.5\times $ of N-TFET, depending on choice of $\mathrm{I}_{\rm OFF}$ and $\mathrm{V}_{\rm DD}$ . There are many challenges to realizing TFETs in products, such as the requirement of high quality III–V materials and oxides with very thin body dimensions, and the TFET’s layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.

357 citations

Journal ArticleDOI
TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

350 citations

Journal ArticleDOI
01 Mar 2021-Nature
TL;DR: In this article, the authors review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking two-dimensional transistors.
Abstract: Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

347 citations