Rushank Suryavanshi

Bio: Rushank Suryavanshi is an academic researcher from VIT University. The author has contributed to research in topics: Serial port & Asynchronous communication. The author has an hindex of 2, co-authored 2 publications receiving 5 citations.

A comparative study of direct digital frequency synthesizer architectures in 180nm CMOS

Abstract: Direct Digital Frequency Synthesizer (DDFS) has long been perceived as a predominant solution for producing precise, variable frequency signals having very low distortion. The paper presents an epigrammatic and a comparative study of direct digital frequency synthesizers architectures. The direct digital frequency synthesizer presented are compared on the basis of two architectures namely, the read only memory (ROM) or look up table based architecture and the other co-ordinate rotation based digital computer that eliminates the usage of the large ROM based look up table. These architectures are compared in terms of the power utilization, SFDR, etc. A mixed signal ASIC designing approach is followed for the implementation approach.

FPGA implementation of universal asynchronous transmitter and receiver

Abstract: The proposed work in this paper describes the implementation of universal asynchronous transmitter and receiver, that is UART. The UART is a type of a serial communication protocol which serves the purpose of full duplex communication over a serial link. The UART here in is described by hardware description language that is Verilog HDL. The Verilog HDL code has been simulated in the ModelSim 10.1d and implemented on Altera DE1 board.

74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations

Abstract: In this brief, a four-stage pipeline read only memory (ROM)-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed. To attain higher spurious-free dynamic range (SFDR) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The second-order parabolic equations with proper coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation using the TSMC 0.18- $\rm {\mu }\text{m}$ CMOS technology cell library and on-silicon measurements, where the maximum SFDR is 74 dBc, 0.018-mW/MHz power dissipation, and the maximal clock frequency is 71.9 MHz.

Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Abstract: A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

High SFDR Pipeline ROM-less DDFS Design on FPGA Platform Using Parabolic Equations

Abstract: A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The parabolic equations with proper selection of coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

Design and Implementation of 1553B Bus Controller on FPGA

Abstract: MIL-STD 1553B serial bus is used in spacecraft for information exchange between subsystems. The three main elements of this 1553B bus are Bus Controller, Remote Terminal and Bus Monitor. This paper describes about the design and implementation of bus controller for a test system that focuses on the Test and Evaluation (T&E) of Onboard Bus interface (1553B) system. The design and implementation is carried out using Quartus 13.1.4 Web Edition on custom made Cyclone III FPGA board.

Multi-Master AMBA AHB Protocol Verification Using TLM Based UVM Environment

Abstract: In the due course of time, due to rising development cost and density of VLSI chips and turnaround time, it turns out to be critical to have a verification methodology, which empowers first pass chips to be entirely functional and error free. Universal Verification Methodology (UVM) facilitates the communication through TLM interface. On account of its excellent architecture of AMBA and simplicity of AHB bus it has been widely used in several SOC designs. This paper is focused on developing a Verification IP (VIP) for Multi-master AMBA AHB protocol using System Verilog based UVM environment. AMBA-AHB provides a high bandwidth system bus which can perform multiple operations in parallel. This project also depicts how Verification IP is used to verify the AHB Components-Arbiter, Slave, Master and Decoder. With the UVM based VIP, it was able to achieve MDV (Metric Driven Verification) and assertion based verification which has drastically minimized the time spent on verification of a design.The Verification IP is developed using Cadence tool Ncsim and can be reused to verify any AHB based system design.