We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

https://calhoun.nps.edu/bitstream/10945/24839/1/singlesidebandtr00elli.pdf

Single sideband transmission by envelope elimination and restoration.

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

Recent trends in the integration of entire systems on-chip have spurred the development of homodyne radios as alternatives to the more mature yet harder to integrate superheterodyne architectures. This paper presents a monolithic device that integrates all of the functions necessary to implement a multiband homodyne global system for mobile telecommunications (GSM) radio except for the power amplifier (PA) and radio frequency (RF) passives. The single BiCMOS chip includes a quad-band direct conversion receiver that down converts RF to quadrature analog baseband. The front-end circuitry is followed by a low-DC-offset, high-dynamic-range, analog I/Q baseband chain. The transmit section is comprised of a quad-band up-conversion transmit phase-locked loop (PLL) including on chip transmit voltage-controlled oscillators (VCOs). The stringent GSM receive band phase noise specifications are met without the use of surface acoustic wave filters. A single /spl Sigma//spl Delta/ fractional-N synthesizer locking a fully integrated ultrahigh frequency VCO generates the system local oscillator signal.

A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.

A polar modulator transmitter for GSM/EDGE

The use of direct conversion receiver topologies has been marked by many technical problems, particularly when used in a TDMA environment. This paper describes a receiver architecture that overcomes many of the traditional problems associated with direct conversion. This architecture has been applied in the design of a GSM multi-band transceiver that also features a development of the offset PLL transmitter together with a fast locking fractional-N synthesizer.

A direct conversion transceiver for multi-band GSM application

A single chip radio transceiver for the DECT (Digital Enhanced Cordless Telephone) system has been implemented using Si 0.6 /spl mu/m BiCMOS technology. The device implements Rx down-converting mixers, a limiting IF strip, second down-converting image rejecting mixer, PLL demodulator with S-field sample and hold, bit slicer, synthesiser, UHF VCO, frequency doubler and transmit buffer. Synthesiser programming and the chip power management is achieved via the programming of an integrated 3 wire serial port. The chip also includes two separate supply voltage regulators, one of which is dedicated for use by the single UHF VCO.

S. Atkinson

Papers

A polar modulator transmitter for GSM/EDGE

A direct conversion transceiver for multi-band GSM application

A single chip radio transceiver for DECT