Bio: S. Bose is an academic researcher from Bell Labs. The author has contributed to research in topics: Sequential logic & Fault (power engineering). The author has an hindex of 8, co-authored 11 publications receiving 164 citations.
••17 Oct 1993
TL;DR: A 23-value logic system is used to generate robust path delay tests that detect as many path faults as possible and select secondary target faults for augmenting the tests to cover multiple faults.
Abstract: We use a 23-value logic system to generate robust path delay tests. Each test is successively augmented to detect as many path faults as possible. Other features of the test generator are a podem-like branch and bound search for test, an efficient path designation based on ordering of paths, and an algorithmic selection of secondary target faults for augmenting the tests to cover multiple faults. Results for ISCAS '89 benchmarks are given. >
••01 Jul 1992
TL;DR: The architecture of the system and the data structures and algorithms for some of the crucial parts of the fault simulation algorithm are outlined and an order of magnitude speed up is indicated compared to a production quality simulator running on a SUN SPARC2.
Abstract: The authors present a concurrent fault simulation algorithm. The pipelined algorithm is suitable for implementation on memory limited hardware accelerators and message passing multicomputers or specialized hardware. The architecture of the system and the data structures and algorithms for some of the crucial parts of the fault simulation algorithm are outlined. For pipelined architectures, fault simulation is illustrated for circuits modeled at mixed functional and gate levels. The results indicate an order of magnitude speed up compared to a production quality simulator running on a SUN SPARC2. >
••20 Sep 1993
TL;DR: The authors present an algorithmic derivation of logic systems for solving path delay test problems and define optimality as to the smallest number of logic states that provide the least possible ambiguity.
Abstract: The authors present an algorithmic derivation of logic systems for solving path delay test problems. In these logic systems, the state of a signal represents any possible situation that can occur during two consecutive vectors. Starting from a set of valid input states, a state transition graph is constructed to enumerate all possible states produced by Boolean gates. Specifics of the test problem are used for distinguishability criteria and to minimize the number of states. For test generation in combinational or sequential circuits, the authors use the algorithm to obtain optimal logic systems. They define optimality as to the smallest number of logic states that provide the least possible ambiguity. The ten-value logic of Fuchs et al. is found to be optimal for generating tests for single path delay faults but gives ambiguous results for multiple path activation. A new 23-value logic is derived as an optimal system for solving the multiple path problem as well as the delay test generation problem of sequential circuits. The limitations and capabilities of various logic systems are illustrated. >
••03 Jan 1993
TL;DR: The present version of this simulator simulates only non-robust faults in synchronous sequential circuits, and results on ISCAS '89 sequential benchmarks using the test patterns generated by a recently published 0.2 algorithm verify the effectiveness of the simulator.
Abstract: To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transilion conditions for two consecutive vectors. APer the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flipflop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The differential fault simulation technique is used to propagate the stored fault effects of previously activated paths. The simulation is independent of the specific delays of the combinational elements and either robust or nonrobust detection can be simulated as an option to the user. However, considering sequential robustness, a path delay fault should be testable irrespective of the delays of all other paths. In that sense, our present version simulates only non-robust faults. Ezperimental results on ISCAS '89 sequential benchmarks using the test patterns generated by a recently published 0.2gorithm verify the effectiveness of the simulator.
TL;DR: A new test generation algorithm provides valid tests for uniform rated-clock test application and derives an optimal 41-valued algebra for three-vector sequences for large circuits for the first time.
Abstract: Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths.
19 Dec 1994
TL;DR: In this article, test vectors for a circuit containing both logic gates and memory blocks are evaluated by applying candidate test vectors to good and faulty versions of the circuit in a computer simulation.
Abstract: Test vectors for a circuit containing both logic gates and memory blocks are evaluated by applying candidate test vectors to good and faulty versions of the circuit in a computer simulation. The functions of the gates and interconnections in the circuit are stored in memory and the operation of the good and faulty circuits is simulated concurrently. During the simulation, a memory record is created for storing the state of a circuit element in a faulty circuit if the fault is visible at the element. Such records are removed when no longer needed, which speeds up the simulation. A multiprocessor in a pipeline configuration is disclosed for performing the simulation. A first branch in the pipeline simulates the logic gates in the circuit; a second branch simulates the memory blocks.
••28 Apr 1996
TL;DR: Various classes of segment delay fault tests are defined that offer a trade-off between fault coverage and quality and are presented as an efficient algorithm to compute the number of segments of any possible length in a circuit.
Abstract: We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.
TL;DR: In this article, the authors examine the developments in IC testing from the historic, current status and future view points and relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.
Abstract: Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal ICs. For many years the market growth and technology advancements in digital ICs were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of mixed-signal ICs. The recent advances in wireless communications indicate a trend toward the integration of the RF and baseband mixed signal technologies. In this paper we examine the developments in IC testing from the historic, current status and future view points. In separate sections we address the testing developments for digital, mixed signal and RF ICs. With these reviews as context, we relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.
••13 Jun 2005
TL;DR: Effective logic soft error protection requires solutions to the following three problems: accurate soft error rate estimation for combinational logic networks; automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected.
Abstract: Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
••21 Oct 1995
TL;DR: This paper classifies path-delay faults into three categories: singly-testable (ST), multiply- testable (MT), and singly -dependent (ST-dependent) by a procedure using any unaltered single stuck fault test generation tool.
Abstract: In this paper, we classify path-delay faults into three categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent (ST-dependent). All ST faults are guaranteed detection in the case of a single fault, and some may be guaranteed detection through robust and validatable non-robust tests even in the case of multiple faults. An ST-dependent fault can affect the circuit speed only if certain ST faults are present. Thus, if the ST faults are tested, the ST-dependent faults need not be tested. MT faults cannot be guaranteed detection, but affect the speed only if delay faults simultaneously exist on a set of paths none of which is ST. We classify all path-delay faults into the three categories by a procedure using any unaltered single stuck fault test generation tool. We use only two runs of this tool on a network derived from the original network. As a by-product of this process, we generate single and multiple input change delay tests for all testable faults. With these tests, we expect that most defective circuits are identified. Examples and results on ISCAS'89 benchmarks are presented.