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S. Crowder

Bio: S. Crowder is an academic researcher from IBM. The author has contributed to research in topics: Silicon on insulator & Copper interconnect. The author has an hindex of 17, co-authored 27 publications receiving 770 citations.

Papers
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Patent
11 Jun 2001
TL;DR: In this article, the authors proposed a process for fabrication of both compact memory and high performance logic on the same semiconductor chip, which consists of forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory and the logic regions, removing the protection layer over the logic region to expose the substrate, and forming the logic device in a logic region.
Abstract: A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

143 citations

Journal ArticleDOI
TL;DR: The key elements within software defined environments include capability-based resource abstraction, goal-based and policy-based workload definition, and outcome-based continuous mapping of the workload to the available resources.
Abstract: During the past few years, enterprises have been increasingly aggressive in moving mission-critical and performance-sensitive applications to the cloud, while at the same time many new mobile, social, and analytics applications are directly developed and operated on cloud computing platforms. These two movements are encouraging the shift of the value proposition of cloud computing from cost reduction to simultaneous agility and optimization. These requirements (agility and optimization) are driving the recent disruptive trend of software defined computing, for which the entire computing infrastructure--compute, storage and network--is becoming software defined and dynamically programmable. The key elements within software defined environments include capability-based resource abstraction, goal-based and policy-based workload definition, and outcome-based continuous mapping of the workload to the available resources. Furthermore, software defined environments provide the tooling and capabilities to compose workloads from existing components that are then continuously and autonomously mapped onto the underlying programmable infrastructure. These elements enable software defined environments to achieve agility, efficiency, and continuous outcome-optimized provisioning and management, plus continuous assurance for resiliency and security. This paper provides an overview and introduction to the key elements and challenges of software defined environments.

75 citations

Patent
09 Nov 2000
TL;DR: In this article, a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible.
Abstract: A method of forming a self-aligned vertical double-gate metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes processing steps that are CMOS compatible. The method include the steps of growing an oxide layer on a surface of a silicon-on-insulator (SOI) substrate, said SOI substrate having a buried oxide region located between a top Si-containing layer and a bottom Si-containing layer, wherein said top and bottom Si-containing layers are of the same conductivity-type; patterning and etching gate openings in said oxide layer, said top Si-containing layer and said buried oxide region stopping on said bottom Si-containing layer of said SOI substrate; forming a gate dielectric on exposed vertical sidewalls of said gate openings and filling said gate openings with silicon; removing oxide on horizontal surfaces which interface with said Si-containing bottom layer; recrystallizing silicon interfaced to said gate dielectric and filling said gate openings with expitaxial silicon; forming a mask on said oxide layer so as cover one of the silicon filled gate openings, while leaving an adjacent silicon filled gate opening exposed; selectively implanting dopants of said first conductivity-type into said exposed silicon filled gate opening and activating the same, wherein said dopants are implanted at an ion dosage of about 1E15 cm −2 or greater; selectively etching the exposed oxide layer and the underlying top Si-containing layer of said SOI substrate stopping on said buried oxide layer; removing said mask and implanting a graded-channel dopant profile in said previously covered silicon filled gate opening; etching any remaining oxide layer and forming spacers about said silicon filled gate openings; and saliciding any exposed silicon surfaces.

64 citations

Proceedings ArticleDOI
06 Dec 1998
TL;DR: In this paper, the authors reported a high performance CMOS operating at 15 V with 119 ps nominal inverter delay at 006/008/spl mu/m L/sub eff/ for NMOS and PMOS.
Abstract: We report a high-performance CMOS operating at 15 V with 119 ps nominal inverter delay at 006/008/spl mu/m L/sub eff/ for NMOS and PMOS Both NMOS and PMOS devices, with 36 nm inversion T/sub ox/, have the best current drive reported to date at fixed I/sub off/ Low-Vt NMOS/PMOS achieved with compensation and with no degradation in short-channel behavior result in nominal 97 ps inverter delay These devices are incorporated in a 018 /spl mu/m technology that offers a 42 /spl mu/m/sup 2/ SRAM cell and dual gate oxide for interfacing to 25 V

47 citations

Patent
08 Jan 2003
TL;DR: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions.
Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

46 citations


Cited by
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Journal ArticleDOI
01 Jan 2015
TL;DR: This paper presents an in-depth analysis of the hardware infrastructure, southbound and northbound application programming interfaces (APIs), network virtualization layers, network operating systems (SDN controllers), network programming languages, and network applications, and presents the key building blocks of an SDN infrastructure using a bottom-up, layered approach.
Abstract: The Internet has led to the creation of a digital society, where (almost) everything is connected and is accessible from anywhere. However, despite their widespread adoption, traditional IP networks are complex and very hard to manage. It is both difficult to configure the network according to predefined policies, and to reconfigure it to respond to faults, load, and changes. To make matters even more difficult, current networks are also vertically integrated: the control and data planes are bundled together. Software-defined networking (SDN) is an emerging paradigm that promises to change this state of affairs, by breaking vertical integration, separating the network's control logic from the underlying routers and switches, promoting (logical) centralization of network control, and introducing the ability to program the network. The separation of concerns, introduced between the definition of network policies, their implementation in switching hardware, and the forwarding of traffic, is key to the desired flexibility: by breaking the network control problem into tractable pieces, SDN makes it easier to create and introduce new abstractions in networking, simplifying network management and facilitating network evolution. In this paper, we present a comprehensive survey on SDN. We start by introducing the motivation for SDN, explain its main concepts and how it differs from traditional networking, its roots, and the standardization activities regarding this novel paradigm. Next, we present the key building blocks of an SDN infrastructure using a bottom-up, layered approach. We provide an in-depth analysis of the hardware infrastructure, southbound and northbound application programming interfaces (APIs), network virtualization layers, network operating systems (SDN controllers), network programming languages, and network applications. We also look at cross-layer problems such as debugging and troubleshooting. In an effort to anticipate the future evolution of this new paradigm, we discuss the main ongoing research efforts and challenges of SDN. In particular, we address the design of switches and control platforms—with a focus on aspects such as resiliency, scalability, performance, security, and dependability—as well as new opportunities for carrier transport networks and cloud providers. Last but not least, we analyze the position of SDN as a key enabler of a software-defined environment.

3,589 citations

Posted Content
TL;DR: Software-Defined Networking (SDN) as discussed by the authors is an emerging paradigm that promises to change this state of affairs, by breaking vertical integration, separating the network's control logic from the underlying routers and switches, promoting (logical) centralization of network control, and introducing the ability to program the network.
Abstract: Software-Defined Networking (SDN) is an emerging paradigm that promises to change this state of affairs, by breaking vertical integration, separating the network's control logic from the underlying routers and switches, promoting (logical) centralization of network control, and introducing the ability to program the network. The separation of concerns introduced between the definition of network policies, their implementation in switching hardware, and the forwarding of traffic, is key to the desired flexibility: by breaking the network control problem into tractable pieces, SDN makes it easier to create and introduce new abstractions in networking, simplifying network management and facilitating network evolution. In this paper we present a comprehensive survey on SDN. We start by introducing the motivation for SDN, explain its main concepts and how it differs from traditional networking, its roots, and the standardization activities regarding this novel paradigm. Next, we present the key building blocks of an SDN infrastructure using a bottom-up, layered approach. We provide an in-depth analysis of the hardware infrastructure, southbound and northbound APIs, network virtualization layers, network operating systems (SDN controllers), network programming languages, and network applications. We also look at cross-layer problems such as debugging and troubleshooting. In an effort to anticipate the future evolution of this new paradigm, we discuss the main ongoing research efforts and challenges of SDN. In particular, we address the design of switches and control platforms -- with a focus on aspects such as resiliency, scalability, performance, security and dependability -- as well as new opportunities for carrier transport networks and cloud providers. Last but not least, we analyze the position of SDN as a key enabler of a software-defined environment.

1,968 citations

Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Journal ArticleDOI
David J. Frank1, R.H. Dennard1, E. J. Nowak1, Paul M. Solomon1, Yuan Taur1, Hon-Sum Philip Wong1 
01 Mar 2001
TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

1,417 citations

Journal ArticleDOI
01 Apr 1997
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

861 citations