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S.D. Sherlekar

Bio: S.D. Sherlekar is an academic researcher from Indian Institute of Technology Bombay. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 3, co-authored 3 publications receiving 41 citations.

Papers
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Proceedings ArticleDOI
26 Nov 1992
TL;DR: The authors suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method.
Abstract: Micropipelines, suggested by Ivan Sutherland (1989) form an elegant scheme for asynchronous implementation of pipelined circuits. The authors analyse the faulty behavior of micropipelines and propose schemes for testing. They suggest that the control part of the micropipeline is concurrently testable during normal operation and that test pattern generation for the data part logic can be reduced to that for combinational circuits, with a simple modification only in the test application method. Testing latches require a two-pattern test which can be generated using test pattern generation techniques for combinational circuits. >

23 citations

Journal ArticleDOI
TL;DR: Two design methods are presented that produce concurrently testable and cascadable combinational blocks for a given logic function that are strongly fault-secure and code-disjoint and have lower hardware overhead.
Abstract: We present two design methods that produce concurrently testable and cascadable combinational blocks for a given logic function. In the first method, the designed block is strongly fault-secure and code-disjoint. Any unordered coding scheme can be used for the input and output. The second method produces designs that are strongly fault-secure and strongly code-disjoint. Here the encoding requires some simple density properties that are seen to be satisfied by the commonly used coding schemes. This makes the method applicable to a larger class of coding schemes than the existing methods. We also show that our designs have lower hardware overhead.

13 citations

Proceedings ArticleDOI
26 Nov 1992
TL;DR: The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function by careful use of such optimizations.
Abstract: The authors present two methods that can be used to reduce the hardware requirement for a self checking implementation of a given combinational function. They give examples to show that these give very significant reduction over the traditional SFS implementation. They believe that by careful use of such optimizations, the size of self checking implementations can be brought down within acceptable limits for use in practice. >

5 citations


Cited by
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Proceedings ArticleDOI
30 Apr 1995
TL;DR: The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor and a method to design and testmicropipelines is presented.
Abstract: The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques.

37 citations

Proceedings ArticleDOI
07 Apr 1997
TL;DR: A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode is presented.
Abstract: An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a two-phase signalling protocol, and the latest release of the AMULET2e embedded controller implemented using four-phase signalling, have proved the practical feasibility of the micropipeline design approach. A built-in self-test (BIST) micropipeline design based on an asynchronous BILBO register is presented in this paper. All the stage registers of the micropipeline are implemented using the proposed asynchronous BILBO register which can operate in four modes: normal operation, shift, linear feedback shift register (LFSR) and signature analyser mode. The test procedure described in this paper provides for the detection of all single stuck-at faults in the micropipeline. It is shown that delay faults in the combinational logic blocks of the BIST micropipeline can be tested by using BLBO registers of a doubled size.

36 citations

Journal ArticleDOI
TL;DR: A new technique for concurrent error detection in finite state machine (FSM) controllers is presented, based on the use of monitoring machines, which yield designs which compare very favourably with previous implementations.
Abstract: In circuits implementing system level functions, the correctness of the overall operation is critically dependent on the correctness of the control part. Therefore, concurrent error detection techniques for controllers implemented in integrated circuits have previously received wide attention. This paper presents a new technique for concurrent error detection in finite state machine (FSM) controllers. It is based on the use of monitoring machines. In a monitored FSM controller, an auxiliary monitoring machine operates in lock-step with the main FSM, such that any fault in either of the two machines is immediately detected. It is shown how the monitoring machine provides a uniform mechanism for the detection of stuck-at faults as well as delay faults. Besides being less costly than the main machine, it is also not identical to it. These features yield designs which compare very favourably with previous implementations. Not only is the fault coverage higher, also the hardware cost of the monitored sequential circuit is significantly lower.

35 citations

Journal ArticleDOI
TL;DR: The objective of this work is to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and to experimentally compare the robustness of both synchronOUS and asynchronous designs.
Abstract: With clock rates beyond 1 GHz, the model of a system wide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called ldquodelay-insensitiverdquo asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.

34 citations

01 Jan 1994
TL;DR: This work presents a technique for testing self-timed micropipelines for stuck-at faults and for delay faults in the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing.
Abstract: Micropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. We present a technique for testing self-timed micropipelines for stuck-at faults and for delay faults in the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing. This scan path allows the processing logic in the micropipeline, as well as the control of the micropipeline, to be fully tested with only a small overhead an the latch and control circuits. The test method is very similar to scan testing in synchronous systems, but the micropipeline retains its self-timed behavior during normal operation.

33 citations