Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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FPGA Architecture: Survey and Challenges

Reliability should be identified as the most important challenge in future nano-scale very large scale integration (VLSI) implementation technologies for the development of complex integrated systems. Normally, fault tolerance (FT) in a conventional system is achieved by increasing its redundancy, which also implies higher implementation costs and lower performance that sometimes makes it even infeasible. In contrast to custom approaches, a new class of applications is categorized in this paper, which is inherently capable of absorbing some degrees of vulnerability and providing FT based on their natural properties. Neural networks are good indicators of imprecision-tolerant applications. We have also proposed a new class of FT techniques called relaxed fault-tolerant (RFT) techniques which are developed for VLSI implementation of imprecision-tolerant applications. The main advantage of RFT techniques with respect to traditional FT solutions is that they exploit inherent FT of different applications to reduce their implementation costs while improving their performance. To show the applicability as well as the efficiency of the RFT method, the experimental results for implementation of a face-recognition computationally intensive neural network and its corresponding RFT realization are presented in this paper. The results demonstrate promising higher performance of artificial neural network VLSI solutions for complex applications in faulty nano-scale implementation environments.

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors

As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPGA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.

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SRAM-Based FPGA Systems for Safety-Critical Applications: A Survey on Design Standards and Proposed Methodologies

Systems working in uncertain environments should possess a robustness property, which ensures that the behaviours of the system remain close to the original behaviours under the influence of unmodeled, but bounded, disturbances. We present a theory and algorithmic tools for the design of robust discrete controllers for π-regular properties on discrete transition systems. Formally, we define metric automata - automata equipped with a metric on states - and strategies on metric automata which guarantee robustness for π-regular properties. We present graph-theoretic algorithms to construct such strategies in polynomial time. In contrast to strategies computed by classical automata-theoretic algorithms, the strategies computed by our algorithm ensure that the behaviours of the controlled system under disturbances satisfy a related property which depends on the magnitude of the disturbance. We show an application of our theory to the design of controllers that tolerate infinitely many transient errors provided they occur infrequently enough.

Robust discrete synthesis against unspecified disturbances

As the feature size shrinks to the nanometer scale, SRAM-based FPGAs will become increasingly vulnerable to soft errors Existing reliability-oriented placement and routing approaches primarily focus on reducing the fault occurrence probability (node error rate) of soft errors However, our analysis shows that, besides the fault occurrence probability, the propagation probability (error propagation probability) plays an important role and should be taken into consideration In this paper, we first propose a cube-based analysis algorithm to efficiently and accurately estimate the error propagation probability Based on such a model, we propose a novel reliability-oriented placement and routing algorithm that combines both the fault occurrence probability and the error propagation probability together to enhance system-level robustness against soft errors Experimental results show that, compared with the baseline versatile place and route technique, the proposed scheme can reduce the failure rate by 2073%, and increase the mean time between failures by 3944%

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with comparable delay, hi addition, in asymmetric SRAM FPGA using our router average FIT (failure-in-time) rate is reduced by 36%.

S. Golshan

Papers

Single-event-upset (SEU) awareness in FPGA routing