S
S.-J. Choi
Researcher at Intel
Publications - 4
Citations - 486
S.-J. Choi is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Low-power electronics. The author has an hindex of 4, co-authored 4 publications receiving 464 citations.
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate
P. Vandervoorn,M. Agostinelli,S.-J. Choi,G. Curello,H. Deshpande,Mohammed A El-Tanani,Hafez Walid M,U. Jalan,L. Janbay,M. Kang,Kwang-Jin Koh,K. Komeyli,Hasnain Lakdawala,J. Lin,Nick Lindert,S. Mudanai,Joodong Park,K. Phoa,Abdur Rahman,Jad B. Rizk,L. Rockford,G. Sacks,Krishnamurthy Soumyanath,H. Tashiro,Stewart S. Taylor,Curtis Tsai,Hongtao Xu,J. Xu,L. Yang,Ian A. Young,J.-Y. Yeh,J. Yip,P. Bai,C.-H. Jan +33 more
TL;DR: A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets.
Proceedings Article
A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB
Ruth A. Brain,Andre Baran,Nabhendra Bisnik,H.-P. Chen,S.-J. Choi,A. Chugh,M. Fradkin,Timothy E. Glassman,F. Hamzaoglu,E. Hoggan,R. Jahan,M. Jamil,C.-H. Jan,J. Jopling,H. Kan,Rahim Kasim,S. Kirby,S. Lahiri,B.-C Lee,Daniel R. Lenski,J. Limb,Nick Lindert,M. Musorrafiti,J. Neulinger,L. Rockford,Joodong Park,Kanwal Jit Singh,C. Staus,Joseph M. Steigerwald,B. Turkot,P. Vandervoorn,R. Venkatesan,Stephen Y. Wu,J.-Y. Yeh,Yih Wang,Z. Zhang,Kevin Zhang +36 more
TL;DR: In this article, a 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices.