Rapid progress in the synthesis and processing of materials with structure on nanometer length scales has created a demand for greater scientific understanding of thermal transport in nanoscale devices, individual nanostructures, and nanostructured materials. This review emphasizes developments in experiment, theory, and computation that have occurred in the past ten years and summarizes the present status of the field. Interfaces between materials become increasingly important on small length scales. The thermal conductance of many solid–solid interfaces have been studied experimentally but the range of observed interface properties is much smaller than predicted by simple theory. Classical molecular dynamics simulations are emerging as a powerful tool for calculations of thermal conductance and phonon scattering, and may provide for a lively interplay of experiment and theory in the near term. Fundamental issues remain concerning the correct definitions of temperature in nonequilibrium nanoscale systems. Modern Si microelectronics are now firmly in the nanoscale regime—experiments have demonstrated that the close proximity of interfaces and the extremely small volume of heat dissipation strongly modifies thermal transport, thereby aggravating problems of thermal management. Microelectronic devices are too large to yield to atomic-level simulation in the foreseeable future and, therefore, calculations of thermal transport must rely on solutions of the Boltzmann transport equation; microscopic phonon scattering rates needed for predictive models are, even for Si, poorly known. Low-dimensional nanostructures, such as carbon nanotubes, are predicted to have novel transport properties; the first quantitative experiments of the thermal conductivity of nanotubes have recently been achieved using microfabricated measurement systems. Nanoscale porosity decreases the permittivity of amorphous dielectrics but porosity also strongly decreases the thermal conductivity. The promise of improved thermoelectric materials and problems of thermal management of optoelectronic devices have stimulated extensive studies of semiconductor superlattices; agreement between experiment and theory is generally poor. Advances in measurement methods, e.g., the 3ω method, time-domain thermoreflectance, sources of coherent phonons, microfabricated test structures, and the scanning thermal microscope, are enabling new capabilities for nanoscale thermal metrology.

/pdf/nanoscale-thermal-transport-1frv881kzm.pdf

Nanoscale thermal transport

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

http://science.sciencemag.org/content/sci/311/5758/208.full.pdf

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

/pdf/3-d-ics-a-novel-chip-design-for-improving-deep-submicrometer-6k9by1rs19.pdf

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.

/pdf/hotspot-a-compact-thermal-modeling-methodology-for-early-43x1muqtv2.pdf

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

/pdf/interconnect-limits-on-gigascale-integration-gsi-in-the-21st-4iloxnfjg6.pdf

Interconnect limits on gigascale integration (GSI) in the 21st century

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.

http://eda.ee.ucla.edu/EE201A-04Spring/3D-overview.pdf

Multiple Si layer ICs: motivation, performance analysis, and design implications

Continuous scaling oc VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor industry roadmap predicts, that beyond the 130 nm technolgy mode, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This papaer presents a comprehensive analytical treatement of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects. This analysis is based on dividing a chip into separate blocks, each occupying a physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Various technologies being investigated for 3-D fabrication are reviewed. Finally, implications of 3-D architecture on several circuit designs are also discussed.

3-D ICs: Motivation, performance analysis, and technology

Interconnect delays are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size. In spite of new materials like Cu with low-k dielectric, interconnect delay is expected to be substantial below 130 nm technology node, thereby severely limiting chip performance unless a paradigm shift from present interconnect architecture is introduced. One such promising technique is three-dimensional ICs with multiple active Si layers and vertical interconnects. This paper presents a comprehensive analytical treatment of 3-D ICs with multiple Si layers. It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs if some long horizontal interconnects can be replaced by short vertical inter-layer interconnects. We also address the thermal concerns due to increased power density for 3-D circuits. It is demonstrated that for circuits with two Silicon layers, acceptable die temperatures can be maintained by either employing thermally responsible circuit designs or by using advanced heat-sinking technologies that would lower the thermal resistance between the chip and the heat sink. Finally, an overview of some of the processing techniques under investigation, which can be used to fabricate these circuits, is reviewed.

S.J. Souri

Papers

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Interconnect limits on gigascale integration (GSI) in the 21st century

Multiple Si layer ICs: motivation, performance analysis, and design implications

3-D ICs: Motivation, performance analysis, and technology

Performance analysis and technology of 3-D ICs