Error coding is a method of detecting and correcting errors that ensures the detection of information bits and error recovery in case of damage. Encoding is done using mathematical techniques that pad extra bits to data which aid the recovery of the original message. Several error coding techniques offering different error rates and recovery capabilities are employed in modern-day communication systems facilitating error-free transmission of information bits. Hardware-based implementations of these error coding techniques for robust memory systems and processors has become imperative due to error resistance compared to their software counterparts. In this work, the authors demonstrate the VERILOG implementation targeted for Artix-7 board, various error coding, and correction methodologies in the view of hardware storage using field programmable gate array (FPGA), thereby providing the readers an insight into the performance and advantages offered by these techniques. Their performance in terms of power consumption and utilization is evaluated and analyzed. 

Implementation of Classical Error Control Codes for Memory Storage Systems Using VERILOG

Data security is becoming a major concern in recent years due to the proliferation of interconnected devices. With the number of devices connected to the Internet of things (IoT) growing at a very rapid pace, design of speed and power efficient crypto systems is very essential. This paper explores the design of a high-speed and low-power advanced encryption standard (AES) architecture to be used as a hardware accelerator in various cryptographic systems. The use of Rijndael S-Box for byte substitution, merging of ShiftRows operation with the State Register updation, implementation of MixColumns transformation through substructure sharing, and clock gating methods are investigated in this work for obtaining a high-speed device with low-power consumption. The proposed design is designed using Verilog and co-simulated in MATLAB and implemented as an ASIC using 90 nm GPDK technology. It is seen that the proposed design has 83% increase in speed, 39% decrease in area, and 82% reduction in power dissipation as compared to a standard AES design implementation. 

Design of a High-Speed and Low-Power AES Architecture

The tremendous increase in information transmission and data storage has lead to a high demand for secure information storage and transfer. Various security services for a wide range of applications use Advanced Encryption Standard (AES) as the default algorithm for encryption. With an ubiquitous access to information through mobile and handheld devices, the need for providing security with minimum area and power consumption is very essential. This paper deals with the design and implementation of a low power and area efficient AES architecture. This is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution. Further reduction in area and power is achieved by using a rotational shift instead of the standard cyclic shifting during the ShiftRow operation. The results from the study indicate that implementation of the proposed design on a Virtex-7 FPGA utilizes 62% less slice registers and 47% less slice LUTs as compared to the standard AES design. Moreover, calculation of power and area in 90 nm GPDK technology results in 30% reduced area and 75% less power.

Low power and area efficient AES implementation using ROM based key expansion and rotational shift

The tremendous increase in information transmission and data storage has lead to a high demand for secure information storage and transfer. Various security services for a wide range of applications use Advanced Encryption Standard (AES) as the default algorithm for encryption. With an ubiquitous access to information through mobile and handheld devices, the need for providing security with minimum area and power consumption is very essential. This paper deals with the design and implementation of a low power and area efficient AES architecture. This is achieved by avoiding the use of registers and using ROM during the sorting operation of AddRound keys and by merging of shift row operation and byte substitution. Further reduction in area and power is achieved by using a rotational shift instead of the standard cyclic shifting during the ShiftRow operation. The results from the study indicate that implementation of the proposed design on a Virtex-7 FPGA utilizes 62% less slice registers and 47% less slice LUTs as compared to the standard AES design. Moreover, calculation of power and area in 90 nm GPDK technology results in 30% reduced area and 75% less power. 

Errors in a transmitted message is unavoidable since noise is inevitable in any communication channel. For reliable transmission of messages, the bit error rate has to be kept at an acceptable rate by the use of proper error control coding schemes. To ensure that the transmission is also secure, data encryption is used as an integral part of the system. This paper deals with the design and analysis of a secure and reliable communication system accomplished using logistic map-based chaotic encryption and turbo product codes. The system is simulated using MATLAB and it is shown that the use of encryption for secure communication does not degrade the system performance. The hardware design of the decoder is also done and verified in Verilog using the same set of vectors as obtained from the system simulation. BER performance was analyzed in all the different scenarios and the correctness of the design was established.

S. Khavya

Papers

Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder