S. M. Farhaduzzaman Azad

Bio: S. M. Farhaduzzaman Azad is an academic researcher from University of Engineering and Technology, Lahore. The author has contributed to research in topics: Gate dielectric & Transistor. The author has an hindex of 2, co-authored 2 publications receiving 27 citations.

Negative Capacitance Tunnel Field Effect Transistor: A Novel Device with Low Subthreshold Swing and High ON Current

Abstract: In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device effectively combines two different mechanisms of lowering the sub threshold swing (SS) for a transistor garnering a further lowered one compared to conventional TFET. A simple yet accurate analytical tunnel current model for the proposed device is also presented here. The developed analytical model demonstrates high ON current at low $V_{GS}$ and exhibits lower SS.

Negative Capacitance Tunnel Field Effect Transistor: A Novel Device with Low Subthreshold Swing and High on Current

Abstract: In this paper we propose a modified structure of TFET incorporating ferroelectric oxide as the complementary gate dielectric operating in negative capacitance zone, called the Negative Capacitance Tunnel FET (NCTFET). The proposed device effectively combines two different mechanisms of lowering the sub threshold swing (SS) for a transistor garnering a further lowered one compared to conventional TFET. A simple yet accurate analytical tunnel drain current model for the proposed device is also presented here. The developed analytical model demonstrates high ON current at low VGS and exhibits lower SS. This paper also provides physics based explanation behind the improvement in the SS for the proposed device over TFET.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Abstract: Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Investigation of Negative Capacitance Gate-all-Around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Abstract: A short-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by integrating three-dimensional (3-D) numerical simulation and the 1D Landau–Khalatnikov equation. It is shown that the NC-GAA-TFET has a steeper subthreshold swing and higher on-state current compared to conventional GAA-TFETs, and demonstrates no hysteretic behavior. Relevant analytical models, including the electrostatic potential model and the shortest tunnel path length ( l sp), are developed to explain the device's operating principles and design optimization issues. Results from the analytical electrostatic potential model agree well with those of the numerical simulation. Furthermore, the analytical calculation shows that gate controllability over the channel is enhanced and the l sp value is significantly reduced as the thickness of the ferroelectric dielectric increases, resulting in better device characteristics. These results demonstrate the tremendous potential of NC-GAA-TFETs in low-power applications.

Proposal of a Hysteresis-Free Zero Subthreshold Swing Field-Effect Transistor

Abstract: An ideal switch with hysteresis-free S ideal = 0 mV/decade switching is desired to keep Moore's law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore's law for 50 years, albeit with a thermodynamically limited value of subthreshold swing S ≥ 60 mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise S <; 60 mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET.