S. Mahajan

Bio: S. Mahajan is an academic researcher from Indian Institute of Technology Bombay. The author has contributed to research in topics: MOSFET. The author has an hindex of 1, co-authored 1 publications receiving 77 citations.

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

Abstract: We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

Abstract: This paper describes various measurements on self-heat performed on Intel's 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability

Abstract: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. 3-D self-consistent electrothermal simulations, tuned with experimentally measured electrical characteristics, were used to understand the nature of self-heating in FinFETs and calibrate the proposed model. The accuracy of the model has been demonstrated for a wide range of multifin devices by comparing it against finite element simulations. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures, which are critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability. The transient model has been used to estimate the thermal time constants of these devices and predict the sensitivity of power-to-failure to various device parameters, for both long and short pulse ESD situations. Suitable modifications to the model are also proposed for evaluating the thermal characteristics of production level FinFET (or Tri-gate FET) structures involving metal-gates, body-tied bulk FinFETs, and trench contacts.

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

Abstract: Thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed in this paper for sub-22-nm technologies using the well-calibrated TCAD simulations. In this paper, we show that bulk FinFETs have a relatively better thermal performance as compared with SOI FinFETs. In order to understand the isothermal characteristics of these devices because of thermal effects, we use pulse rise-time as well as ac conductance methods. We demonstrate that the ac conductance method fails to accurately capture thermal time constants for FinFETs, as self-heating and gate resistance regions are indistinguishable from each other. A pulse rise-time method gives isothermal characteristics of these devices. As verified from both these independent techniques, only at high frequencies (>1 GHz), FinFETs show a suppression of thermally induced degradation, which can be attributed to their higher surface-to-volume ratio. It is observed that bulk FinFETs will perform better than SOI FinFETs for small effective fin heights. However, as we show in this paper, increased body doping in bulk FinFETs will increase the self-heating effects. Channel length scaling in FinFETs, which shows a decrease in drain current degradation with heating, will be an important design parameter for sub-22-nm devices.

3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature

Abstract: Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, $\Delta T(x,y,z; t)$ , at the NW level is important for predicting activity-induced variability within an IC, as well as characterization of various reliability issues, such as, NBTI, PBTI, HCI, and TDDB that depend sensitively on self-heating. In this paper, a 3-D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in GAA devices. Our results identify complex heat dissipation pathways characterized by multiple time constants. First, the nanowires heat up quickly ( $\tau _{\textrm {GAA-NW}}\sim \textrm {nSec}$ ), then heat spreads all over the gate contact pad ( $\tau _{\textrm {G-pad}}\sim 100$ nSec), and finally, the heat exits through the heat sink at the bottom of the substrate ( $\tau _{\textrm {sub}}\sim \textrm {mSec}$ ). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices.

Freely scalable and reconfigurable optical hardware for deep learning

Abstract: As deep neural network (DNN) models grow ever-larger, they can achieve higher accuracy and solve more complex problems This trend has been enabled by an increase in available compute power; however, efforts to continue to scale electronic processors are impeded by the costs of communication, thermal management, power delivery and clocking To improve scalability, we propose a digital optical neural network (DONN) with intralayer optical interconnects and reconfigurable input values The near path-length-independence of optical energy consumption enables information locality between a transmitter and arbitrarily arranged receivers, which allows greater flexibility in architecture design to circumvent scaling limitations In a proof-of-concept experiment, we demonstrate optical multicast in the classification of 500 MNIST images with a 3-layer, fully-connected network We also analyze the energy consumption of the DONN and find that optical data transfer is beneficial over electronics when the spacing of computational units is on the order of >10 micrometers