S. Mehrmanesh

Bio: S. Mehrmanesh is an academic researcher from Sharif University of Technology. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 7, co-authored 20 publications receiving 119 citations.

A 1-volt, high PSRR, CMOS bandgap voltage reference

Abstract: A low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.25 um CMOS technology, with a power supply of 1 volt. The results show PSRR is below -70 dB at 1 MHz and the output voltage variation versus temperature (0-70) is less than 0.3%. This circuit shows robustness against process variation.

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

Abstract: In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18 /spl mu/m CMOS process show a THD of less than -44dB for 0.6V/sub pp/ input signal and an input-referred noise of less than 45 nV//spl radic/Hz in worst case. The current consumption of each OTA is 1.5-mA.

A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity

Abstract: A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. The improved dynamic linearity at high frequencies, a low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to a 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18/spl mu/m CMOS technology.

A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters

Abstract: A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology.

An ultra low-voltage Gm-C filter for video applications

Abstract: A new, ultra low-voltage, linear CMOS OTA is described. A 4/sub th/ order, 18 MHz low pass Butterworth Gm-C filter has been designed with this new OTA stage for video applications. In this filter, a new, fully digital approach has been used for frequency tuning. The THD of the filter, for an input signal of 0.5 V/sub PP/, is better than -60 dB. All of the circuits are designed based on a 0.25 /spl mu/m CMOS process technology with a single 1 V power supply.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

Abstract: A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented The proposed DCC has been rubricated in a TSMC 035mum standard CMOS process An input duty cycle range of 30%~70% is achieved The duty cycle error is within plusmn10% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications The chip area is merely 03 x 02 mm2 and the power consumption is 1 1mW at 550 MHz

A general framework for evaluating nonlinearity, noise and dynamic range in continuous‐time OTA‐C filters for computer‐aided design and optimization

Abstract: Efficient procedures for evaluating nonlinear distortion and noise valid for any OTA-C filter of arbitrary order are developed based on matrix description of a general OTA-C filter model. Since those procedures use OTA macromodels, they allow us to obtain the results significantly faster than transistor-level simulation. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. Due to this, the proposed procedures can be used in direct optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. As an example, a simple optimization procedure using equivalence transformations is discussed. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter is given. Accuracy of the theoretical tools has been verified by comparing to transistor-level simulation results and to experimental results. Copyright © 2006 John Wiley & Sons, Ltd.

Methods and arrangements to adjust a duty cycle

Abstract: Methods and arrangements to adjust a duty cycle of a clock signal are disclosed. Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.