S. Pae

Bio: S. Pae is an academic researcher from Intel. The author has contributed to research in topics: Computer science & Copper interconnect. The author has an hindex of 1, co-authored 1 publications receiving 921 citations.

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology

Abstract: With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.

Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs

Abstract: With the growth of high-speed computing memory, the HBM (High Bandwidth Memory) has been developed using advanced process technologies including high-k and metal gate process for the interfacing logic chip and 3D DRAM stack structures with TSV connections. This paper reviews overall reliability of the advanced HBM with 17nm DRAM process from device level to product level. This includes the product aging focused on logic buffer die and environmental reliability of the integrated multi-layer structure. Intrinsic FEOL and BEOL reliability such as TDDB, NBTI and EM were demonstrated >10 years of lifetime. Ni/Cu UBM (Under Bump Material) improved EM lifetime by $\boldsymbol{15\mathrm{x}}$ compared to the previous Ni UBM. In addition, a novel package test method considering mechanical stress on 2.5D SiP (silicon in package) enabled the interconnect reliability including TSV/micro bump EM and package environmental tests level to be evaluated more precisely. Reliability of HBM with 17nm high-k metal gate process showed robustness and meets 10yrs lifetime with HTOL over 1000hrs aging, hot temperature storage, temperature humidity bias and precondition including multiple cycles of IR reflow for production.

Development and Product Reliability Characterization of Advanced High Speed 14nm DDR5 DRAM with On-die ECC

Abstract: The reliability characterization of fabricated 14nm DDR5 DRAMs with On-die Error Correction Code (ECC) and EUV process is presented for the first time. Intrinsic reliability of FEOL and BEOL WLR showed well above 10yrs of lifetime, 125°C. The products demonstrated no fails in high temperature operating lifetime (HTOL) of 1000hrs. The On-Die ECC design improved the single bit error rate by $\boldsymbol{10^{-6}}$ times (refresh time $\boldsymbol{ > 4\mathrm{x}}$). The failure rate, ppm of manufacturing burn-in process confirmed the healthiness of the baseline material and also effectively screen out and monitor any random defects. The presented 14nm DDR5 DRAMs are well in production for the PC segments and have been shipping and qualified for the Server segments.

Single-layer MoS2 transistors

Abstract: Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.

Electronics based on two-dimensional materials

Abstract: The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Integrated Circuits and Logic Operations Based on Single-Layer MoS2

Abstract: Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS2 represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS2. Our integrated circuits are capable of operating as inverters, converting logical “1” into logical “0”, with room-temperature voltage gain higher than 1, making them suitable for incorporat...

Two-dimensional semiconductors for transistors

Abstract: In the quest for higher performance, the dimensions of field-effect transistors (FETs) continue to decrease. However, the reduction in size of FETs comprising 3D semiconductors is limited by the rate at which heat, generated from static power, is dissipated. The increase in static power and the leakage of current between the source and drain electrodes that causes this increase, are referred to as short-channel effects. In FETs with channels made from 2D semiconductors, leakage current is almost eliminated because all electrons are confined in atomically thin channels and, hence, are uniformly influenced by the gate voltage. In this Review, we provide a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FETs in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene. We also describe tunnelling FETs that possess extremely low-power switching behaviour and explain how they can be realized using heterostructures of 2D semiconductors. Field-effect transistors (FETs) with semiconducting channels made from 2D materials are known to have fewer problems with short-channel effects than devices comprising 3D semiconductors. In this Review, a mathematical framework to evaluate the performance of FETs is outlined with a focus on the properties of 2D materials, such as graphene, transition metal dichalcogenides, phosphorene and silicene.

Graphene and two-dimensional materials for silicon technology.

Abstract: The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.