ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

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SOI for digital CMOS VLSI: design considerations and advances

This paper discusses state-of-the-art electrostatic discharge (ESD) protection in advanced semiconductor technologies and emerging technologies. ESD physics, semiconductor process issues, device and circuit simulation, circuits, and devices are examined.

The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

Substrate pump NMOS for ESD protection applications

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work.

Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

The design and optimization of ESD protection circuits is greatly enhanced by the ability to perform circuit-level simulations of the protection circuits and the I/O buffers. Most available simulators do not cover the high current region of the circuit operation, but still enable an approximate analysis to be made of the behaviour under ESD conditions. In this article, a description of the behaviour of the MOS device in the high current regime is presented together with the model equations governing that behaviour. The equations have been implemented into a SPICE circuit simulator, and the experimental and simulation results are given. A simple parameter extraction methodology is presented that uses the terminal currents from a single MOS DC I-V curve to obtain all the MOS and bipolar parameters required for the model.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

This paper establishes the critical ESD design issues for a partially depleted 0.35 /spl mu/m SOI process. Through device analysis we show for the first time that the gate bias of an NMOS during ESD plays a critical role in reducing channel heating and in achieving good protection levels for both positive and negative stress polarities. With an optimum design window, we demonstrate greater than /spl plusmn/2 kV ESD performance with no additional process steps.

https://ieeexplore.ieee.org/iel5/3767/11001/00507849.pdf

S. Ramaswamy

Papers

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high-current simulations

ESD design for deep submicron SOI technology [NMOS transistor]