S
S. Ramey
Researcher at Intel
Publications - 38
Citations - 1626
S. Ramey is an academic researcher from Intel. The author has contributed to research in topics: Reliability (semiconductor) & Transistor. The author has an hindex of 15, co-authored 34 publications receiving 1444 citations.
Papers
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Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
Intrinsic transistor reliability improvements from 22nm tri-gate technology
S. Ramey,A. Ashutosh,C. Auth,J. Clifford,Michael L. Hattendorf,J. Hicks,Robert James,Anisur Rahman,Vyom Sharma,A. St. Amour,Christopher J. Wiegand +10 more
TL;DR: In this article, the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process, are highlighted.
Proceedings ArticleDOI
BTI reliability of 45 nm high-K + metal-gate process technology
S. Pae,M. Agostinelli,M. Brazier,R. Chau,G. Dewey,Tahir Ghani,Michael L. Hattendorf,J. Hicks,Jack Portland Kavalieros,K. Kuhn,Markus Kuhn,J. Maiz,Matthew V. Metz,Kaizad Mistry,Chetan Prasad,S. Ramey,A. Roskowski,J. Sandford,C. Thomas,J. Thomas,Christopher J. Wiegand,J. Wiedemer +21 more
TL;DR: In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed.
Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Proceedings ArticleDOI
Transistor aging and reliability in 14nm tri-gate technology
S. Novak,C. Parker,D. Becher,Mark Y. Liu,M. Agostinelli,M. Chahal,Paul A. Packan,P. Nayak,S. Ramey,Sanjay Natarajan +9 more
TL;DR: The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.