S.S. Gong

Bio: S.S. Gong is an academic researcher from Motorola. The author has contributed to research in topics: Gate oxide & Oxide. The author has an hindex of 1, co-authored 1 publications receiving 36 citations.

Evaluation of Q/sub bd/ for electrons tunneling from the Si/SiO/sub 2/ interface compared to electron tunneling from the poly-Si/SiO/sub 2/ interface

Abstract: Electrical time-to-breakdown (TTB) measurements have shown the charge to breakdown Q/sub bd/ of gate oxide capacitors fabricated on n-type well (n-well) substrates always to be higher than that of capacitors on p-type well (p-well) substrates on the same wafer when both are biased into accumulation under normal test conditions. Here the authors correlate the higher n-well Q/sub bd/ to smooth capacitor oxide/substrate interfaces and minimized grain boundary cusps at the poly-Si gate/oxide interfaces, confirming that Fowler-Nordheim tunneling is the dominant current conduction mechanisms through the oxide. They correlate higher Q/sub bd/ to higher barrier height for a given substrate type and observe that the slope of the barrier height versus temperature plot is lower for both p-well and n-well cases with electrons tunneling from the silicon substrate. This is attributed to surface roughness at the poly-Si gate/SiO/sub 2/ interface. A poly-Si gate deposition and annealing process with clean, smooth oxide/substrate interfaces will improve the p-well breakdown characteristics and allow higher Q/sub bd/ to be achieved. >

Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM

Abstract: The degradation of thin tunnel gate oxide under constant Fowler-Nordheim (FN) current stress was studied using flash EEPROM structures. The degradation is a strong function of the amount of injected charge density (Q/sub inj/), oxide thickness, and the direction of stress. Positive charge trapping is usually dominant at low Q/sub inj/ followed by negative charge trapping at high Q/sub inj/, causing a turnaround of gate voltage and threshold voltage. Interface trap generation continues to increase with increasing stress, as evidenced by subthreshold slope and transconductance. Gate injection stress creates more positive charge traps and interface traps than does substrate injection stress. Oxide degradation gets more severe for thicker oxide, due to more oxide charge trapping and interface trap generation by impact ionization. A simple model of oxide degradation and breakdown was established based on the experimental results. It indicates that the damage in the oxide is more serious near the anode interface by impact ionization and oxide breakdown is also closely related to surface roughness at the cathode interface. When all the damage sites in the oxide connect and a conductive path between cathode and anode is formed, oxide breakdown occurs. The damage is more serious for thicker oxide because a thicker oxide is more susceptible to impact ionization.

Effect of physical stress on the degradation of thin SiO/sub 2/ films under electrical stress

Abstract: In this work, we demonstrate that for ultrathin MOS gate oxides, the reliability is closely related to the SiO/sub 2//Si interfacial physical stress for constant current gate injection (V/sub g//sup -/) in the Fowler-Nordheim tunneling regime. A physical stress-enhanced bond-breaking model is proposed to explain this. The oxide breakdown mechanism is very closely related to the Si-Si bond formation from the breakage of Si-O-Si bond, and that is influenced by the physical stress in the film. The interfacial stress is generated due to the volume expansion from Si to SiO/sub 2/ during the thermal oxidation, and it is a strong function of growth conditions, such as temperature, growth rate, and growth ambient. Higher temperatures, lower oxidation rates, and higher steam concentrations allow faster stress relaxation through viscous flow. Reduced disorder at the interface results in better reliability. Fourier transform infrared spectroscopy (FTIR) technique has been used to characterize stress in thin oxide films grown by both furnace and rapid thermal process (RTP). In conjunction with the Gibbs free energy theory, this model successfully predicts the trends of time-to-breakdown (t/sub bd/) as a function of oxide thickness and growth conditions. The trends of predicted t/sub bd/ values agree well with the experimental data from the electrical measurement.

Enhanced Fowler-Nordheim tunneling effect in nanocrystallite Si based LED with interfacial Si nano-pyramids

Abstract: The premier observation on the enhanced light emission from such a metal-SiOx-Si light emitting diode (MOSLED) with Si nano-pyramids at SiOx/Si interface is demonstrated at low biases. The Si nano-pyramids exhibits capability in providing the roughness of the SiOx/Si interface, and improving the Fowler-Nordheim (F-N) tunneling mechanism based carrier injection through the novel SiOx/nano-Si-pyramid/Si structure. HRTEM analysis reveals a precisely controllable size and concentration of the crystallized interfacial Si nano-pyramids at 10nm(height)×10nm(width) and within the range of 108-1011 cm-2, respectively. With these Si nano-pyramids at a surface density of up to 1012/cm2, the F-N tunneling threshold can be reduce from 7 MV/cm to 1.4 MV/cm. The correlation between surface density of the interfacial Si nano-pyramids and the threshold F-N tunneling field has been elucidated. Such a turn-on reduction essentially provides a less damaged SiOx/Si interface as the required bias for the electroluminescence of the MOSLED is greatly decreased, which thus suppresses the generation of structural damage related radiant defects under a lower biased condition and leads to a more stable near-infrared electroluminescence with a narrowing linewidth and an operating lifetime lengthened to >3 hours. An output EL power of nearly 150 nW under a biased voltage of 75 V and current density of 32 mA/cm2 is reported for the first time.

A complete model of E/sup 2/PROM memory cells for circuit simulations

Abstract: E/sup 2/PROM memory devices are widely used in embedded applications For an efficient design flow, a correct modeling of these memory cells in every operation condition becomes more and more important, especially due to power consumption limitations Although E/sup 2/PROM cells have being used for a long time, very few compact models have been developed Here, we present a complete compact model based on an original procedure to calculate the floating gate potential in DC conditions, without the need of any capacitive coupling coefficient This model is designed as a modular structure, so to simplify program/erase and reliability simulations Program/erase and leakage currents are included by means of simple voltage-controlled current sources implementing their analytical expression It can be used to simulate memory cells both during read operation (DC conditions) and during program and erase (transient conditions) giving always very accurate results We show also that, provided there are good descriptions of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation