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S. Satheesh Kumar

Researcher at VIT University

Publications -  7
Citations -  38

S. Satheesh Kumar is an academic researcher from VIT University. The author has contributed to research in topics: Transistor & Single event upset. The author has an hindex of 2, co-authored 7 publications receiving 30 citations.

Papers
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Journal ArticleDOI

Isolation and characterization of tyrosinase produced by marine actinobacteria and its application in the removal of phenol from aqueous environment

TL;DR: The enzyme efficiently removed the phenolic compounds from aqueous solution within few hours which indicated that tyrosinase enzyme produced by Streptomyces espinosus strain LK-4 can be potently used for the removal of phenol and phenolic compound from wastewater in industries.
Book ChapterDOI

Fault Tolerant Cloud Systems

TL;DR: Monitoring the resources helps in measuring the performance of the cloud so that the resource can be provisioned to customers efficiently and has a vital impact on resource provision.
Book ChapterDOI

A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module

TL;DR: This paper studies the operation and working of a Dual Dynamic node hybrid flip-flop (DDFF-ELM) with an embedded logic module that is one of the most efficient D-Flip-flops in terms of power and delay as compared to other dynamic flip flops.
Proceedings ArticleDOI

SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology

TL;DR: The proposed soft-error tolerant flip flop utilizes a cross-coupled inverter on the critical path in the master-stage and generates the required differential signals to facilitate the usage of the Quarto soft- error tolerant cell in the slave-stage.
Journal ArticleDOI

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

TL;DR: In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes and is highly immune to single and multi-node upsets, demonstrating that the proposed latch achieves high low power and low area results.