S. Simon Wong

Bio: S. Simon Wong is an academic researcher from Stanford University. The author has contributed to research in topics: CMOS & Electromigration. The author has an hindex of 49, co-authored 265 publications receiving 10285 citations. Previous affiliations of S. Simon Wong include Cornell University & Hong Kong University of Science and Technology.

On-chip spiral inductors with patterned ground shields for Si-based RF ICs

Abstract: This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor.

Physical modeling of spiral inductors on silicon

Abstract: This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance.

A physical model for planar spiral inductors on silicon

Abstract: This paper presents a physical model for planar spiral inductors on silicon. The model has been confirmed with measured and published data of inductors having different geometric and process parameters. This model is scalable with inductor geometry, allowing designers to predict and optimize the quality factor.

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

Abstract: Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

Phonon-boundary scattering in thin silicon layers

Abstract: Temperature fields in microdevices made from silicon-on-insulator (SOI) wafers are strongly influenced by the lateral thermal conductivity of the silicon overlayer, which is diminished by phonon scattering on the layer boundaries. This study measures the thermal conductivity of single-crystal silicon layers in SOI substrates at temperatures between 20 and 320 K using Joule heating and electrical-resistance thermometry in microfabricated structures. Data for layers of thickness between 0.4 and 1.6 μm demonstrate the large reduction resulting from phonon-boundary scattering, particularly at low temperatures, and are consistent with predictions based on the phonon Boltzmann transport equation.

Nanoionics-based resistive switching memories

Abstract: Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

Enhanced thermoelectric performance of rough silicon nanowires

Abstract: Approximately 90 per cent of the world's power is generated by heat engines that use fossil fuel combustion as a heat source and typically operate at 30-40 per cent efficiency, such that roughly 15 terawatts of heat is lost to the environment. Thermoelectric modules could potentially convert part of this low-grade waste heat to electricity. Their efficiency depends on the thermoelectric figure of merit ZT of their material components, which is a function of the Seebeck coefficient, electrical resistivity, thermal conductivity and absolute temperature. Over the past five decades it has been challenging to increase ZT > 1, since the parameters of ZT are generally interdependent. While nanostructured thermoelectric materials can increase ZT > 1 (refs 2-4), the materials (Bi, Te, Pb, Sb, and Ag) and processes used are not often easy to scale to practically useful dimensions. Here we report the electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20-300 nm in diameter. These nanowires have Seebeck coefficient and electrical resistivity values that are the same as doped bulk Si, but those with diameters of about 50 nm exhibit 100-fold reduction in thermal conductivity, yielding ZT = 0.6 at room temperature. For such nanowires, the lattice contribution to thermal conductivity approaches the amorphous limit for Si, which cannot be explained by current theories. Although bulk Si is a poor thermoelectric material, by greatly reducing thermal conductivity without much affecting the Seebeck coefficient and electrical resistivity, Si nanowire arrays show promise as high-performance, scalable thermoelectric materials.

Memristive devices for computing

Abstract: Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Nanoscale thermal transport

Abstract: Rapid progress in the synthesis and processing of materials with structure on nanometer length scales has created a demand for greater scientific understanding of thermal transport in nanoscale devices, individual nanostructures, and nanostructured materials. This review emphasizes developments in experiment, theory, and computation that have occurred in the past ten years and summarizes the present status of the field. Interfaces between materials become increasingly important on small length scales. The thermal conductance of many solid–solid interfaces have been studied experimentally but the range of observed interface properties is much smaller than predicted by simple theory. Classical molecular dynamics simulations are emerging as a powerful tool for calculations of thermal conductance and phonon scattering, and may provide for a lively interplay of experiment and theory in the near term. Fundamental issues remain concerning the correct definitions of temperature in nonequilibrium nanoscale systems. Modern Si microelectronics are now firmly in the nanoscale regime—experiments have demonstrated that the close proximity of interfaces and the extremely small volume of heat dissipation strongly modifies thermal transport, thereby aggravating problems of thermal management. Microelectronic devices are too large to yield to atomic-level simulation in the foreseeable future and, therefore, calculations of thermal transport must rely on solutions of the Boltzmann transport equation; microscopic phonon scattering rates needed for predictive models are, even for Si, poorly known. Low-dimensional nanostructures, such as carbon nanotubes, are predicted to have novel transport properties; the first quantitative experiments of the thermal conductivity of nanotubes have recently been achieved using microfabricated measurement systems. Nanoscale porosity decreases the permittivity of amorphous dielectrics but porosity also strongly decreases the thermal conductivity. The promise of improved thermoelectric materials and problems of thermal management of optoelectronic devices have stimulated extensive studies of semiconductor superlattices; agreement between experiment and theory is generally poor. Advances in measurement methods, e.g., the 3ω method, time-domain thermoreflectance, sources of coherent phonons, microfabricated test structures, and the scanning thermal microscope, are enabling new capabilities for nanoscale thermal metrology.