Bio: S. Sivanantham is an academic researcher from VIT University. The author has contributed to research in topics: Automatic test pattern generation & Verilog. The author has an hindex of 8, co-authored 49 publications receiving 207 citations.
TL;DR: Two multistage compression techniques to reduce the test data volume in scan test applications and the simple decoder architecture to decode the original data are presented.
Abstract: In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.
••21 Jul 2011
TL;DR: This paper proposes low power reconfigurable multiplier architecture based reordering of partial products, which reduces the power consumption based on partial products reordering.
Abstract: In any general purpose processor the use of conventional full precision multipliers results in increase in the power, area and computational time. So, multipliers being the basic key element of any computation unit take its own importance in decreasing the power as well as increase in the speed. Twin Precision Multipliers has flexible and reconfigurable computational units are creating a trend which overcomes the drawback of the conventional full precision multipliers and also resulting in higher computational throughput of the processors. This paper proposes low power reconfigurable multiplier architecture based reordering of partial products, which reduces the power consumption based on partial products reordering. Reordering of partial products technique is applied on both High Performance Multiplication (HPM) and Dadda column reduction techniques to obtain low power reconfigurable twin precision multiplier.
••01 Nov 2015
TL;DR: This paper presents the design of 16*16 Modified Booth multiplier which performs both signed and unsigned multiplication and used Carry Select Adder it increases the speed of multiplier operation.
Abstract: The Modified Booth multiplier is attractive to many multimedia and digital signal processing systems. This paper presents the design of 16∗16 Modified Booth multiplier. The multipliers such as Braun array multiplier and Array multiplier are used for unsigned multiplication. This paper focusing on design of Modified Booth Multiplier which performs both signed and unsigned multiplication. Here used Carry Select Adder it increases the speed of multiplier operation. Booth encoder multiplier with Carry select Adder utilizes the minimum hardware, reduced chip area, low power dissipation and reduced the cost of the system.
TL;DR: The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells and divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which provides better run length for test data reduction.
Abstract: In this paper, we present a hybrid X-filling and two-stage test data compression (TS-TDC) techniques for digital VLSI circuits to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based Huffman Coding (RLHC) since ASRL codewords contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76% compression ratio for ISCAS’89 benchmark circuits.
TL;DR: There is a need to protect digital documents from authorized users who try to redistribute it illegally.
Abstract: Nowadays, the use of digital content or digital media is increasing day by day. Therefore, there is a need to protect the digital document from both unauthorized users and authorized users. The digital document should be protected from authorized users who try to redistribute it illegally. Digital watermarking techniques along with cryptography are insufficient to ensure an adequate level of security of digital media. The security of the transferring digital data in the modern world is also a big challenge because there is a high risk of security breaches. In this article, a secure technique of image fusion using hybrid domains (spatial and frequency) for privacy preserving and copyright protection is proposed. The proposed method provides a secure technique for the digital content in cloud environment. Two cloud services are used to develop this work, which eliminates the role of a trusted third party (TTP). First is the design of an infrastructure as a service (IaaS) to store different images with encryption processes to speed up the image fusion process and save storage space. Second, a Platform as a Service (PaaS) is used to enable the digital content to improve computation power and to increase the bandwidth. The prime objective of the proposed scheme is to transfer the digital media between a service provider and customer in a secure way using a hybrid domain along with cloud storage. Imperceptibility and robustness measures are used to calculate the performance of the proposed approach.
TL;DR: This work proposes an AI-enabled framework for automating cleaning tasks through a Human Support Robot (HSR), and the overall cleaning process involves mobile base motion, door-handle detection, and control of the HSR manipulator for the completion of the cleaning tasks.
Abstract: The role of mobile robots for cleaning and sanitation purposes is increasing worldwide. Disinfection and hygiene are two integral parts of any safe indoor environment, and these factors become more critical in COVID-19-like pandemic situations. Door handles are highly sensitive contact points that are prone to be contamination. Automation of the door-handle cleaning task is not only important for ensuring safety, but also to improve efficiency. This work proposes an AI-enabled framework for automating cleaning tasks through a Human Support Robot (HSR). The overall cleaning process involves mobile base motion, door-handle detection, and control of the HSR manipulator for the completion of the cleaning tasks. The detection part exploits a deep-learning technique to classify the image space, and provides a set of coordinates for the robot. The cooperative control between the spraying and wiping is developed in the Robotic Operating System. The control module uses the information obtained from the detection module to generate a task/operational space for the robot, along with evaluating the desired position to actuate the manipulators. The complete strategy is validated through numerical simulations, and experiments on a Toyota HSR platform.
••24 Jun 2018
TL;DR: This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library that provides higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers.
Abstract: The architectural differences between ASICs and FPGAs limit the effective performance gains achievable by the application of ASIC-based approximation principles for FPGA-based reconfigurable computing systems. This paper presents a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library. Our designs provide higher area, latency and energy gains along with better output accuracy than those offered by the state-of-the-art ASIC-based approximate multipliers. Moreover, compared to the multiplier IP offered by the Xilinx Vivado, our proposed design achieves up to 30%, 53%, and 67% gains in terms of area, latency, and energy, respectively, while incurring an insignificant accuracy loss (on average, below 1% average relative error). Our library of approximate multipliers is open-source and available online at https://cfaed.tudresden.de/pd-downloads to fuel further research and development in this area, and thereby enabling a new research direction for the FPGA community.
TL;DR: Generic area-optimized, low-latency accurate, and approximate softcore multiplier architectures, which exploit the underlying architectural features of FPGAs, i.e., lookup table (LUT) structures and fast-carry chains to reduce the overall critical path delay (CPD) and resource utilization of multipliers
Abstract: Multiplication is one of the widely used arithmetic operations in a variety of applications, such as image/video processing and machine learning FPGA vendors provide high-performance multipliers in the form of DSP blocks These multipliers are not only limited in number and have fixed locations on FPGAs but can also create additional routing delays and may prove inefficient for smaller bit-width multiplications Therefore, FPGA vendors additionally provide optimized soft IP cores for multiplication However, in this work, we advocate that these soft multiplier IP cores for FPGAs still need better designs to provide high-performance and resource efficiency Towards this, we present generic area-optimized, low-latency accurate and approximate softcore multiplier architectures, which exploit the underlying architectural features of FPGAs, ie, look-up table (LUT) structures and fast carry chains to reduce the overall critical path delay and resource utilization of multipliers Compared to Xilinx multiplier LogiCORE IP, our proposed unsigned and signed accurate architecture provides up to 25% and 53% reduction in LUT utilization, respectively, for different sizes of multipliers Moreover, with our unsigned approximate multiplier architectures, a reduction of up to 51% in the critical path delay can be achieved with an insignificant loss in output accuracy when compared with the LogiCORE IP For illustration, we have deployed the proposed multiplier architecture in accelerators used in image and video applications, and evaluated them for area and performance gains Our library of accurate and approximate multipliers is open-source and available online at https://cfaedtu-dresdende/pd-downloads to fuel further research and development in this area, facilitate reproducible research, and thereby enabling a new research direction for the FPGA community