Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

https://www.mdpi.com/1424-8220/20/18/5165/pdf

Hardware Trojans in Chips: A Survey for Detection and Prevention.

In today's world, as the demand for IC production grows exponentially, testing and validation of all the manufactured chips becomes impossible Therefore, in the proposed method, we have developed a technique for embedding unique signatures with minimalistic hardware or area overhead while preserving the intended functionality To achieve this, three ‘levels’ of security are provided First, circuit specific information is derived and used for signature generation Second, the generated signature is hashed, obfuscating the logic reverse engineering process and finally a bit sequence from a Pseudo-Random Number Generator (PRNG) to make it unfeasibly difficult for the attacker to decode the signature

BHARKS: Built-in hardware authentication using random key sequence

Traditional learning-based approaches for runtime hardware Trojan (HT) detection require complex and expensive on-chip data acquisition frameworks, and thus incur high area and power overhead. To address these challenges, we propose to leverage the power correlation between the executing instructions of a microprocessor to establish a machine learning (ML)-based runtime HT detection framework, called MacLeR. To reduce the overhead of data acquisition, we propose a single power-port current acquisition block using current sensors in time-division multiplexing, which increases accuracy while incurring reduced area overhead. We have implemented a practical solution by analyzing multiple HT benchmarks inserted in the RTL of a system-on-chip (SoC) consisting of four LEON3 processors integrated with other IPs, such as vga_lcd, RSA, AES, Ethernet, and memory controllers. Our experimental results show that compared to state-of-the-art HT detection techniques, MacLeR achieves 10% better HT detection accuracy (i.e., 96.256%) while incurring a $7\times $ reduction in area and power overhead (i.e., 0.025% of the area of the SoC and $\approx 10\times $ less than in the case of the state-of-the-art ML-based HT detection technique.

MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices

SIMCom: Statistical sniffing of inter-module communications for runtime hardware trojan detection

Rapid developments in the field of cryptography and hardware security have increased the need for random number generators which are not only of low-complexity but are also secure to the point of being undeterminable A random number generator is a part of most security systems, so it should be simple and area efficient Many modern-day pseudorandom number generators (PRNGs) make use of linear feedback shift registers (LFSRs) Though these PRNGs are of low complexity, they fall short when it comes to being secure since they are not truly random in nature Thus, in this chapter we propose a random seeding LFSR-based truly random number generator (TRNG) which is not only of low complexity, like the aforementioned PRNGs, but is also ‘truly random’ in nature Our proposed design generates an n-bit truly random number sequence that can be used for a variety of hardware security based applications Based on our proposed n-bit TRNG design, we illustrate an example which generates 16-bit truly random sequences, and a detailed analysis is shown based on National Institute of Standards and Technology (NIST) tests to highlight its randomness

Random seeding LFSR-based TRNG for hardware security applications

Virtual instrumentation is a powerful tool that has been largely left unexplored in the domain of hardware security. It facilitates creation of automated tests to detect the presence of Trojans in a circuit thereby reducing the chance of human errors and the time required for testing. The presence of a stealthy Trojan in large VLSI circuits could lead to leakage of confidential information even in high-security applications such as defense equipment. Here, we propose the usage of virtual instrumentation to detect the presence of a delay-based Trojan in a circuit. Our results confirm that VI-based systems provide a cheap, self-sufficient, easy-to-use interface, and flexible scheme which can be easily modified to accommodate any VLSI circuit. This can also be used in other detection techniques without the need for use of complex systems.

S. Vallinayagam

Papers

Delay-Based Reference Free Hardware Trojan Detection Using Virtual Intelligence