S. Wijesuriya

Bio: S. Wijesuriya is an academic researcher from Alcatel-Lucent. The author has contributed to research in topics: Fault (power engineering) & Programmable logic device. The author has an hindex of 1, co-authored 1 publications receiving 156 citations.

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications

Abstract: In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

Dynamic fault tolerance in FPGAs via partial reconfiguration

Abstract: In this paper we present an on-line, multi-level fault tolerant (FT) technique for system functions and applications mapped to partially and dynamically reconfigurable FPGAs. Our method is based on the roving self testing areas (STARs) fault detection/location strategy presented in Abramovici et al. (1999). In STARs, the area under test uses partial reconfiguration properties to modify the configuration of the area under test without affecting the configuration of the system function and dynamic reconfiguration properties to allow uninterrupted execution of the system function while reconfiguration takes place. In this paper we take this one step further. Once a fault (or multiple faults) is detected we dynamically reconfigure the working area application around the fault with no additional system function interruption (other than the interruption when a STAR moves to a new location). We also apply the concept of partially usable blocks to increase fault tolerance. Our method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.

BIST-based test and diagnosis of FPGA logic blocks : Reconfigurable and Adaptive VLSI Systems

Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

BIST-based test and diagnosis of FPGA logic blocks

Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

Reconfigurable architecture for autonomous self-repair

Abstract: Fault-tolerant systems typically require expensive additional resources (spare pins, columns, and chips) and external control for reconfiguration. We introduce an effective, low-cost repair solution in which originally unused blocks and routing resources replace faulty parts. In addition, the proposed reconfiguration hardware allows autonomous repair, that is, the system does not require external intervention for recovery.

Online Fault Tolerance for FPGA Logic Blocks

Abstract: Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration