S.Y. Wang

Bio: S.Y. Wang is an academic researcher from Hewlett-Packard. The author has contributed to research in topics: Authentication & Nanoimprint lithography. The author has an hindex of 8, co-authored 22 publications receiving 430 citations.

One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography

Abstract: We have developed a process to fabricate a cross-bar structure using UV-curable nanoimprint lithography with a UV-curable double-layer spin-on resist, metal lift off and Langmuir–Blodgett film deposition. This process allowed us to produce 1-kbit cross-bar memory circuits at 30-nm half-pitch on both top and bottom electrodes. Read, write, erase and cross talking were also investigated.

A smooth optical superlens

Abstract: We demonstrate a smooth and low loss silver (Ag) optical superlens capable of resolving features at 1/12th of the illumination wavelength with high fidelity. This is made possible by utilizing state-of-the-art nanoimprint technology and intermediate wetting layer of germanium (Ge) for the growth of flat silver films with surface roughness at subnanometer scales. Our measurement of the resolved lines of 30 nm half-pitch shows a full-width at half-maximum better than 37 nm, in excellent agreement with theoretical predictions. The development of this unique optical superlens leads promise to parallel imaging and nanofabrication in a single snapshot.

Growth and characterization of indium phosphide single-crystal nanoneedles on microcrystalline silicon surfaces

Abstract: The epitaxial growth of nanometer-scale structures on non-single crystalline surfaces is proposed and demonstrated. Hydrogenated amorphous silicon was deposited onto an SiO2 surface by plasma-enhanced chemical vapor deposition. Indium phosphide was deposited on the amorphous silicon by low-pressure metalorganic chemical vapor deposition in the presence of colloidal gold particles as catalysts. Under specific growth conditions, the indium phosphide formed nanoneedles connected to a microcrystalline silicon film nucleated within the amorphous silicon during the growth of the nanoneedles. Transmission electron microscopy revealed the presence of two different crystallographic structures: zinc-blende and wurtzite. Micro-photoluminescence measurements at room temperature showed two peaks with substantial blue-shifts with respect to that of bulk zinc-blende indium phosphide.

Ultra-smooth metal surfaces generated by pressure-induced surface deformation of thin metal films

Abstract: We present a mechanical pressing technique for generating ultra-smooth surfaces on thin metal films by flattening the bumps, asperities, rough grains and spikes of a freshly vacuum deposited metal film. The method was implemented by varying the applied pressure from 100 MPa to 600 MPa on an e-beam evaporated silver film of thickness 1000 A deposited on double-polished (100)-oriented silicon surfaces, resulting in a varying degree of film smoothness. The surface morphology of the thin film was studied using atomic force microscopy. Notably, at a pressure of ∼600 MPa an initial silver surface with 13-nm RMS roughness was plastically deformed and transformed to an ultra-flat plane with better than 0.1 nm RMS. Our demonstration with the e-beam evaporated silver thin film exhibits the potential for applications in decreasing the scattering-induced losses in optical metamaterials, plasmonic nanodevices and electrical shorts in molecular-scale electronic devices.

Ultra-smooth platinum surfaces for nanoscale devices fabricated using chemical mechanical polishing

Abstract: A technique involving two steps of chemical mechanical polishing (CMP) has been developed to produce ultra-smooth metal surfaces with an RMS roughness better than 0.1 nm. A figure of merit termed degree of smoothness (DOS) is proposed for the purpose of quantifying the extent of smoothness of a polished metal surface. A post CMP metal slurry cleaning solution was used for cleaning Pt slurry for the first time and by applying special techniques, a very high quality clean surface was attained. Applications of the polished Pt electrodes in interfacing molecular switching devices with self-assembled monolayers of molecules have been found to dramatically improve the packing and orientation of the molecular monolayer with a huge improvement in the molecular electronics device yields. These smooth metal surfaces may open doors for new opportunities in future nanoscale devices.

Nanoionics-based resistive switching memories

Abstract: Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

Alternative Plasmonic Materials: Beyond Gold and Silver

Abstract: Materials research plays a vital role in transforming breakthrough scientific ideas into next-generation technology. Similar to the way silicon revolutionized the microelectronics industry, the proper materials can greatly impact the field of plasmonics and metamaterials. Currently, research in plasmonics and metamaterials lacks good material building blocks in order to realize useful devices. Such devices suffer from many drawbacks arising from the undesirable properties of their material building blocks, especially metals. There are many materials, other than conventional metallic components such as gold and silver, that exhibit metallic properties and provide advantages in device performance, design flexibility, fabrication, integration, and tunability. This review explores different material classes for plasmonic and metamaterial applications, such as conventional semiconductors, transparent conducting oxides, perovskite oxides, metal nitrides, silicides, germanides, and 2D materials such as graphene. This review provides a summary of the recent developments in the search for better plasmonic materials and an outlook of further research directions.

Nanoelectronics from the bottom up

Abstract: Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core-shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.

A 160-kilobit molecular electronic memory patterned at 10 11 bits per square centimetre

Abstract: The primary metric for gauging progress in the various semiconductor integrated circuit technologies is the spacing, or pitch, between the most closely spaced wires within a dynamic random access memory (DRAM) circuit. Modern DRAM circuits have 140 nm pitch wires and a memory cell size of 0.0408 mum(2). Improving integrated circuit technology will require that these dimensions decrease over time. However, at present a large fraction of the patterning and materials requirements that we expect to need for the construction of new integrated circuit technologies in 2013 have 'no known solution'. Promising ingredients for advances in integrated circuit technology are nanowires, molecular electronics and defect-tolerant architectures, as demonstrated by reports of single devices and small circuits. Methods of extending these approaches to large-scale, high-density circuitry are largely undeveloped. Here we describe a 160,000-bit molecular electronic memory circuit, fabricated at a density of 10(11) bits cm(-2) (pitch 33 nm; memory cell size 0.0011 microm2), that is, roughly analogous to the dimensions of a DRAM circuit projected to be available by 2020. A monolayer of bistable, [2]rotaxane molecules served as the data storage elements. Although the circuit has large numbers of defects, those defects could be readily identified through electronic testing and isolated using software coding. The working bits were then configured to form a fully functional random access memory circuit for storing and retrieving information.