Solar-energy conversion usually takes one of two forms: the 'quantum' approach, which uses the large per-photon energy of solar radiation to excite electrons, as in photovoltaic cells, or the 'thermal' approach, which uses concentrated sunlight as a thermal-energy source to indirectly produce electricity using a heat engine. Here we present a new concept for solar electricity generation, photon-enhanced thermionic emission, which combines quantum and thermal mechanisms into a single physical process. The device is based on thermionic emission of photoexcited electrons from a semiconductor cathode at high temperature. Temperature-dependent photoemission-yield measurements from GaN show strong evidence for photon-enhanced thermionic emission, and calculated efficiencies for idealized devices can exceed the theoretical limits of single-junction photovoltaic cells. The proposed solar converter would operate at temperatures exceeding 200 degrees C, enabling its waste heat to be used to power a secondary thermal engine, boosting theoretical combined conversion efficiencies above 50%.

http://absimage.aps.org/image/MAR10/MWS_MAR10-2009-006451.pdf

Photon Enhanced Thermionic Emission for Solar Concentrator Systems

This paper reviews the fundamental concepts and the terminology of wetting. In particular, it focuses on high temperature wetting phenomena of primary interest to materials scientists. We have chosen to split this review into two sections: one related to macroscopic (continuum) definitions and the other to a microscopic (or atomistic) approach, where the role of chemistry and structure of interfaces and free surfaces on wetting phenomena are addressed. A great deal of attention has been placed on thermodynamics. This allows clarification of many important features, including the state of equilibrium between phases, the kinetics of equilibration, triple lines, hysteresis, adsorption (segregation) and the concept of complexions, intergranular films, prewetting, bulk phase transitions versus “interface transitions”, liquid versus solid wetting, and wetting versus dewetting.

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A review of wetting versus adsorption, complexions, and related phenomena: the rosetta stone of wetting

In this work, the electrical characteristics of different atomic layer deposited high-permittivity dielectric films (Al2O3, HfO2, and a nanolaminate of them), with a physical thickness of about 10 nm, are evaluated. An extensive capacitance-voltage and current-voltage characterization at room temperature is carried out on metal-insulator-semiconductor structures fabricated on different p-type and n-type silicon substrates and with Al as metal gate. HfO2 layers are found to exhibit the higher dielectric constant, but they suffer from the largest hysteresis and leakage currents and the lowest breakdown voltages. The nanolaminate stacks, with an intermediate dielectric constant, are found to exhibit more similarities to the Al2O3 layers, withstanding the largest voltages of all the studied dielectric films. The electrical degradation of the layers is evaluated by means of consecutive current-voltage ramps and with constant voltage stress experiments. Results on n-type Si, with electron injection from the sub...

Electrical characteristics of metal-insulator-semiconductor structures with atomic layer deposited Al2O3, HfO2, and nanolaminates on different silicon substrates

An effective method to generate traps at the interface was developed to enhance the charge trapping capability of HfO2/Al2O3 multilayered memory devices. A high charge density was obtained in the inter-diffusion layer in which additional trap sites could be created by thermal-treatment induced inter-diffusion. By keeping the consistent thickness of the charge trapping layer and increasing the number of the inter-diffusion layers, more traps can be introduced in the charge trapping layer. So, creating more trap sites by enhancing the inter-diffusion at the interface of different high-k dielectrics could be a potential choice for future memory applications.

The interface inter-diffusion induced enhancement of the charge-trapping capability in HfO2/Al2O3 multilayered memory devices

The electronic structures and transport properties of group IV atoms (C, Si, Ge)-doped armchair phosphorene nanoribbons (APNRs) are investigated using first-principles calculations, considering different edge passivation. The results show that the C, Si, Ge dopants can induce the transition occur from semiconductor to metal in the APNRs. The negative differential resistance (NDR) behavior in the doped APNR system is robust with respect to the doping concentration and edge passivation type. However, their current peak positions and peak-to-valley ratio (PVR) values are correlated with doping concentration and edge passivation type. In particular, for the C, Si-doped APNRs, the low bias NDR behavior with the PVR (105–108) can be observed when doping concentration is low in the APNRs with the F and H edge passivation. These results may play an important role for the fabrication of future low power consumption nano-electronic devices.

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Modulation of electronic transport properties in armchair phosphorene nanoribbons by doping and edge passivation.

We demonstrate a low voltage nonvolatile memory field effect transistor comprising thermal SiO2 tunneling and HfO2 blocking layers as the gate dielectric stack and Au nanocrystals as charge storage nodes. The structure exhibits a memory window of ∼2 V at an applied sweeping voltage of ±3 V which increases to 12.6 at ±12 V. Retention tests show an extrapolated loss of 16% after ten years in the hysteresis width of the threshold voltage. Dynamic program/erase operation reveal an approximately pulse width independent memory for pulse durations of 1 μs to 10 ms; longer pulses increase the memory window while for pulses shorter than 1 μs, the memory windows vanishes. The effective oxide thickness is below 10 nm with very low gate and drain leakage currents.

Nonvolatile low-voltage memory transistor based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals

Ultrathin dielectric capping layers are a prominent route for threshold voltage control in advanced Si devices. In this work the position of an Al2O3 layer inside a HfO2-based stack is systematically varied and investigated following a low and a high temperature anneal. Electrical results are compared with a sub-nanometer resolution materials characterization, showing a diffusion of Al to the bottom HfO2 interface. A correlation is found between the presence of Al at the bottom interface and a flatband voltage increase. Based on these findings, we propose to use the position of the Al2O3 for fine-tuning the threshold voltage.

Investigation of the band offsets caused by thin Al2O3 layers in HfO2 based Si metal oxide semiconductor devices

A high sensitivity photo-detector operating in the 245 to 880 nm wavelength range is reported. It is based on a planar Metal-Oxide-Semiconductor (MOS) structure fabricated on an insulator on silicon substrate where the insulator layer comprises a double layer dielectric stack of SiO2-HfO2. The MOS detector undergoes a voltage stress process after which it exhibits a record high responsivity of 0.4 A/W at 500–600 nm and 0.1 A/W at the spectrum edges, 245 and 880 nm. The structure is significantly simpler to fabricate than P-N or P-I-N junction devices and offers a lower dark current than Metal-Semiconductor-Metal diodes. Oxygen vacancies induced in the HfO2 sub-layer by the voltage stress form the conduction paths of the photo generated carriers. The penetration, under reverse bias conditions, of holes originating in the Si depletion layer is improved under illumination since their potential barrier is lowered. The compatibility with complimentary MOS technology processes makes this new structure attractive for many applications.

A highly sensitive broadband planar metal-oxide-semiconductor photo detector fabricated on a silicon-on-insulator substrate

We present a metal-insulator-semiconductor nonvolatile memory capacitor based on two gold nanoparticle charge storage layers, two Hf0 2 layers, and a multilayer HfNO/HfTiO stack. The device exhibits an equivalent oxide thickness of 7.3 nm, a hysteresis of 15 V at a gate voltage of +11 to -8 V, and a storage charge density of 2.75 × 10 13 cm -2 . A leakage of 3.6 × 10- 5 A/cm 2 at -10 V, a breakdown voltage of 13.3 V, and good retention properties with a hysteresis window of 10 V following more than 10 h of consecutive write/erase operations with a ±7 V swing were demonstrated. The capacitor characteristics are frequency-independent in the 10 kHz-1 MHz range.

A Nonvolatile Memory Capacitor Based on a Double Gold Nanocrystal Storing Layer and High-k Dielectric Tunneling and Control Layers

We report on the structural and electrical characteristics of non-volatile memory (NVM) transistors and capacitors that use Pt nanocrystals (NCs) for charge storage. The transistor exhibits a memory window of 0.6 V for a sweep of ±2.5 V which increases to 11.5 V at ±10 V. The trapped charges (electron and hole) density for a ±10 V write/erase signal are 2.9 × 1013 cm−2. At small source to drain voltages (VSD) and for delay times longer than 0.1 ms, negative differential resistance (NDR) type behavior of the transistor source to drain ISD-VSD characteristics is revealed. The physical mechanism responsible for the NDR is related to the dynamics of electron injection (by tunneling through the thin bottom oxide) and their trapping by the Pt NCs. The large storage capability and relatively low program/erase voltages as well as the use of Pt, that is a Fab friendly material, make the described NVM transistors promising for practical applications.

S. Yofis

Papers

Nonvolatile low-voltage memory transistor based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals

Investigation of the band offsets caused by thin Al2O3 layers in HfO2 based Si metal oxide semiconductor devices

A highly sensitive broadband planar metal-oxide-semiconductor photo detector fabricated on a silicon-on-insulator substrate

A Nonvolatile Memory Capacitor Based on a Double Gold Nanocrystal Storing Layer and High-k Dielectric Tunneling and Control Layers

Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance