S. Zanella

Bio: S. Zanella is an academic researcher from PDF Solutions. The author has contributed to research in topics: Clock skew & Logic gate. The author has an hindex of 6, co-authored 9 publications receiving 291 citations. Previous affiliations of S. Zanella include University of Padua.

Designing an integrated circuit to improve yield using a variant design element

Abstract: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

Abstract: A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.

Analysis of the impact of process variations on clock skew

Abstract: In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.

Impact analysis of process variability on clock skew

Abstract: This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew. The methodology is divided in three phases. The first phase is a topological analysis used to screen non-critical network configurations, which does not require computationally expensive steps such as parasitic extraction and circuit-level simulation. The second phase is a detailed nominal skew computation based on accurate 3D extraction, performed on a small set of configurations identified as critical by the topological analysis. The third phase is a variational analysis of the impact of process variations and design parameters on the clock skew, that might induce timing margin violations. This methodology has been implemented for scan chain analysis and validated on an industrial strength test case.

Modeling of substrate noise injected by digital libraries

Abstract: Switching noise is one of the major sources of timing errors and functional hazards in logic circuits. It is caused by the cumulative effect of microscopic spurious currents arising in all devices during logic transitions. These currents are injected into the substrate and in supply lines, resulting in significant ripple noise. Individually, such micro-currents do not usually cause catastrophic failures. However, cumulatively, they can impact power supply and substrate potential across the chip. Thus, the electrical behavior of sensitive digital and analog circuits can be significantly changed, hence limiting circuit performance. The analysis of switching noise at a macroscopic level requires one to accurately compute models for all microscopic spurious currents, known as noise signatures. The challenge is to simultaneously account for a myriad of parameters and their process variations in a compact and accurate model. To address this problem, a new methodology based on response surface methodology and orthogonal polynomial approximation is proposed. Experimental results on a 0.35 /spl mu/m library show that the methodology is capable of accurately approximating noise signatures with a single analytical formula. A library of such formulae has been created and it is being used to accurately characterize switching noise at the macroscopic level.

The Design and Analysis of Experiments

Abstract: THE DESIGN AND ANALYSIS OF EXPERIMENTS. By Oscar Kempthorne. New York, John Wiley and Sons, Inc., 1952. 631 pp. $8.50. This book by a teacher of statistics (as well as a consultant for \"experimenters\") is a comprehensive study of the philosophical background for the statistical design of experiment. It is necessary to have some facility with algebraic notation and manipulation to be able to use the volume intelligently. The problems are presented from the theoretical point of view, without such practical examples as would be helpful for those not acquainted with mathematics. The mathematical justification for the techniques is given. As a somewhat advanced treatment of the design and analysis of experiments, this volume will be interesting and helpful for many who approach statistics theoretically as well as practically. With emphasis on the \"why,\" and with description given broadly, the author relates the subject matter to the general theory of statistics and to the general problem of experimental inference. MARGARET J. ROBERTSON

A general probabilistic framework for worst case timing analysis

Abstract: The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a fundamentally different framework that aims to significantly improve the accuracy of timing predictions through fully probabilistic analysis of gate and path delays. We describe a bottom-up approach for the construction of joint probability density function of path delays, and present novel analytical and algorithmic methods for finding the full distribution of the maximum of a random path delay space with arbitrary path correlations.

Electronic devices and systems, and methods for making and using the same

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Device Modeling for Analog and RF CMOS Circuit Design: Ytterdal/Device

Abstract: Preface. MOSFET Device Physics and Operation. MOSFET Fabrication. RF Modeling. Noise Modeling. Proper Modeling for Accurate Distortion Analysis. The BSIM4 MOSFET Model. The EKV Model. Other MOSFET Models. Bipolar Transistors in CMOS Technologies. Modeling of Passive Devices. Effects and Modeling of Process Variation and Device Mismatch. Quality Assurance of MOSFET Models. Index.

Rapid Yield Estimation and Optimization of Microwave Structures Exploiting Feature-Based Statistical Analysis

Abstract: In this paper, we propose a simple, yet reliable methodology to expedite yield estimation and optimization of microwave structures. In our approach, the analysis of the entire response of the structure at hand (e.g., $S$ -parameters as a function of frequency) is replaced by response surface modeling of suitably selected feature points. On the one hand, this is sufficient to determine whether a design satisfies given performance specifications. On the other, by exploiting the almost linear dependence of the feature points on the designable parameters of the structure, reliable yield estimates can be realized at low computational cost. Our methodology is verified using two examples of waveguide filters and one microstrip hairpin filter and compared with conventional Monte Carlo analysis based on repetitive electromagnetic simulations, as well as with statistical analysis exploiting linear response expansions around the nominal design. Finally, we perform yield-driven design optimizations on these filters.