Sabrina E. Kemeny

TL;DR: In this paper, an imaging device is formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary MOS semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate and a charge coupled device section formed on the substrate adjacent the photrogate having a sensing node connected to the output transistor and at least one charge coupled

TL;DR: In this paper, a family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported.

TL;DR: In this paper, a 2.0 /spl mu/m double-poly, double-metal foundry CMOS active pixel image sensor is reported, which uses TTL compatible voltages, low noise and large dynamic range, and is useful in machine vision and smart sensor applications.

TL;DR: In this paper, an active pixel sensor (APS) is integrated on a CMOS chip with the timing and control circuits, and signal conditioning to enable random access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms).

TL;DR: In this paper, an imaging device consisting of a monolithic complementary metal oxide semiconductor integrated circuit is presented, which includes a focal plane array of pixel cells (10), each one of the cells including a photogate (12) overlying the substrate (20) for accumulating photo-generated charge in an underlying portion of the substrate and a CCD device section (14) formed on the substrate adjacent the photogates (12), having a sensing node and at least one charge coupled device stage (16) for transferring charge from the underlying portion to the sensing node.