Author

# Sachin S. Sapatnekar

Other affiliations: IBM, Association for Computing Machinery, San Francisco State University ...read more

Bio: Sachin S. Sapatnekar is an academic researcher from University of Minnesota. The author has contributed to research in topics: Routing (electronic design automation) & Electronic circuit. The author has an hindex of 56, co-authored 424 publications receiving 12543 citations. Previous affiliations of Sachin S. Sapatnekar include IBM & Association for Computing Machinery.

##### Papers published on a yearly basis

##### Papers

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09 Nov 2003

TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.

Abstract: We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parameter variations, using a method based on principal component analysis. The method uses a PERT-like circuit graph traversal, and has a run-time that is linear in the number of gates and interconnects, as well as the number of grid partitions used to model spatial correlations. On average, the mean and standard deviation values computed by our method have errors of 0.2% and 0.9%, respectively, in comparison with a Monte Carlo simulation.

561 citations

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27 Mar 2006TL;DR: A simple solution to recover the SNM of the SRAM cell using a data flipping technique is proposed and the results simulated on BPTM 70nm and 100nm technology are presented.

Abstract: Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious effects on transistor threshold voltage. The degradation of PMOS devices due to NBTI leads to reduced temporal performance in digital circuits. We have analyzed the impact of NBTI on the read stability of SRAM cells. The amount of degradation in Static Noise Margin (SNM), which is a measure of the read stability of the 6-T SRAM cell has been estimated using Reaction-Diffusion (R-D) model. We propose a simple solution to recover the SNM of the SRAM cell using a data flipping technique and present the results simulated on BPTM 70nm and 100nm technology. We also compare and evaluate different implementation methodologies for the proposed technique.

340 citations

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TL;DR: An efficient convex optimization algorithm is used here, guaranteed to find the exact solution to the convex programming problem, and improved upon existing methods for computing the circuit delay as an Elmore time constant to achieve higher accuracy.

Abstract: A general sequential circuit consists of a number of combinational stages that lie between latches For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results An efficient convex optimization algorithm has been used here This algorithm is guaranteed to find the exact solution to the convex programming problem We have also improved upon existing methods for computing the circuit delay as an Elmore time constant, to achieve higher accuracy, CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm >

301 citations

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TL;DR: This paper presents a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid, and shows that even for a 60 million-node power grid, the approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

Abstract: Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.

284 citations

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TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra- die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented.

Abstract: Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations The accuracy of the method is verified with Monte Carlo (MC) simulation On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 106% and -434%, respectively, and the errors of predicting the 99% and 1% confidence point are -246% and -099%, respectively A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h

276 citations

##### Cited by

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[...]

TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.
Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

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TL;DR: This book by a teacher of statistics (as well as a consultant for "experimenters") is a comprehensive study of the philosophical background for the statistical design of experiment.

Abstract: THE DESIGN AND ANALYSIS OF EXPERIMENTS. By Oscar Kempthorne. New York, John Wiley and Sons, Inc., 1952. 631 pp. $8.50. This book by a teacher of statistics (as well as a consultant for \"experimenters\") is a comprehensive study of the philosophical background for the statistical design of experiment. It is necessary to have some facility with algebraic notation and manipulation to be able to use the volume intelligently. The problems are presented from the theoretical point of view, without such practical examples as would be helpful for those not acquainted with mathematics. The mathematical justification for the techniques is given. As a somewhat advanced treatment of the design and analysis of experiments, this volume will be interesting and helpful for many who approach statistics theoretically as well as practically. With emphasis on the \"why,\" and with description given broadly, the author relates the subject matter to the general theory of statistics and to the general problem of experimental inference. MARGARET J. ROBERTSON

13,333 citations

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20 Sep 2004

1,387 citations

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TL;DR: This tutorial paper collects together in one place the basic background material needed to do GP modeling, and shows how to recognize functions and problems compatible with GP, and how to approximate functions or data in a formcompatible with GP.

Abstract: A geometric program (GP) is a type of mathematical optimization problem characterized by objective and constraint functions that have a special form. Recently developed solution methods can solve even large-scale GPs extremely efficiently and reliably; at the same time a number of practical problems, particularly in circuit design, have been found to be equivalent to (or well approximated by) GPs. Putting these two together, we get effective solutions for the practical problems. The basic approach in GP modeling is to attempt to express a practical problem, such as an engineering analysis or design problem, in GP format. In the best case, this formulation is exact; when this is not possible, we settle for an approximate formulation. This tutorial paper collects together in one place the basic background material needed to do GP modeling. We start with the basic definitions and facts, and some methods used to transform problems into GP format. We show how to recognize functions and problems compatible with GP, and how to approximate functions or data in a form compatible with GP (when this is possible). We give some simple and representative examples, and also describe some common extensions of GP, along with methods for solving (or approximately solving) them.

1,215 citations

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TL;DR: The Gottesman-Knill theorem, which says that a stabilizer circuit, a quantum circuit consisting solely of controlled-NOT, Hadamard, and phase gates can be simulated efficiently on a classical computer, is improved in several directions.

Abstract: The Gottesman-Knill theorem says that a stabilizer circuit\char22{}that is, a quantum circuit consisting solely of controlled-NOT (CNOT), Hadamard, and phase gates\char22{}can be simulated efficiently on a classical computer. This paper improves that theorem in several directions. First, by removing the need for Gaussian elimination, we make the simulation algorithm much faster at the cost of a factor of 2 increase in the number of bits needed to represent a state. We have implemented the improved algorithm in a freely available program called CHP (CNOT-Hadamard-phase), which can handle thousands of qubits easily. Second, we show that the problem of simulating stabilizer circuits is complete for the classical complexity class $\ensuremath{\bigoplus}\mathsf{L}$, which means that stabilizer circuits are probably not even universal for classical computation. Third, we give efficient algorithms for computing the inner product between two stabilizer states, putting any $n$-qubit stabilizer circuit into a ``canonical form'' that requires at most $O({n}^{2}∕\mathrm{log}\phantom{\rule{0.2em}{0ex}}n)$ gates, and other useful tasks. Fourth, we extend our simulation algorithm to circuits acting on mixed states, circuits containing a limited number of nonstabilizer gates, and circuits acting on general tensor-product initial states but containing only a limited number of measurements.

969 citations