In this brief, a low-complexity and novel technique is proposed to efficiently implement the address generation circuitry of the 2-D deinterleaver used in the WiMAX transreceiver using the Xilinx field-programmable gate array (FPGA). The floor function associated with the implementation of the steps, required for the permutation of the incoming bit stream in channel interleaver/deinterleaver for IEEE 802.16e standard is very difficult to implement in FPGA. A simple algorithm along with its mathematical background developed in this brief, eliminates the requirement of floor function and thereby allows low-complexity FPGA implementation. The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying, 16-quadrature-amplitude modulation (QAM), and 64-QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. The proposed approach exhibits significant improvement in the use of FPGA resources. Exhaustive simulation has been carried out to claim supremacy of our proposed work.

Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver

In the recent past, the IEEE 802.11 based wireless LAN has emerged as a prevailing broadband indoor networking technology. Fast spread of wireless data communication systems and the ever increasing demand for faster data rates require quick design, implementation and test of new wireless algorithms for data communications. In this paper we present a novel technique to model the interleaver used in IEEE 802.11a and IEEE 802.11g based WLAN in VHDL using Xilinx ISE. Our proposed technique comprises of finite state machine (FSM) based address generator and FPGA's internal resource based memory. The FSM based approach provides higher operating frequency and better FPGA resource utilization. Use of FPGA's embedded memory offers advantages like reduced access time, lesser occupancy of circuit board and lower power consumption than external memory based techniques. The interleaver memory is modeled using two different types of embedded memory; one with dedicated and the other with distributed memory. Comparative analysis between the two techniques has been made in respect of use of FPGA's internal resources, maximum operating frequency and power consumption. The simulation result obtained using ModelSim XE-III software is also presented.

Design of a Novel FSM Based Reconfigurable Multimode Interleaver for WLAN Application

Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex. In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates. The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2015.0070

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

WiMAX technology aims to provide wireless metropolitan area transmissions with guaranteed quality of service. Towards this aim, sophisticated channel encoding techniques must be implemented in a hardware, which is optimized for such techniques. In this context, this article presents the design of a channel encoder for mobile WiMAX networks, which is prototyped in reconfigurable hardware architecture.The validation of the prototype was conducted considering scheduled traffic in the medium access control layer. Results showed that the channel encoder is fundamental for guaranteeing quality of service in mobile WiMAX networks. Keywords: Channel Encoding Block, Reconfigurable Hardware, WiMAX.

Channel Encoding Block for Mobile WiMAX Networks Using Reconfigurable Hardware

A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.

Convolutional interleaver for bursty memory access

Wireless technology is the fastest growing segment of the modern communication industry. The IEEE 802.16e standard, commonly known as mobile WiMAX, is the latest wireless technology that has promised to offer Broadband Wireless Access over long distance. The concept of OFDM is used in WiMAX to obtain high data rate in addition to reducing the effects like inter symbol interference and inter channel interference. It has proved to be the air interface for next generation Broadband Wireless System. In this paper, we present a finite state machine based novel technique to model the Address Generation circuitry of WiMAX multimode interleaver using VHDL on FPGA platform with all code rates and modulation schemes of IEEE 802.16e standard. Our approach provides better performance in terms of maximum operating frequency, use of flip-flops with negligible loss in terms of logic cells utilized compared to existing FPGA based implementations. Measured circuit parameters and software simulation of this model are also provided.

Novel design of Address Generator for WiMAX multimode interleaver using FPGA based finite state machine

The Analog-to-Digital Converter (ADC), with its wide variety of applications in the electronics and communication domains, is the most crucial unit in every digital gadget. This paper discusses a smart way of converting an input analog signal to its digital counterpart using an innovative Adaptive-Delta modulator, followed by a signal reconstruction process to retrieve the original message. It has done the design in Matrix Laboratory (MATLAB) Simulink, and the hardware implementation is tested on the Xilinx Spartan-6 LX45 FPGA core. This design aims for high-accuracy conversion and optimization of hardware resources. The 1-bit adaptive model is superior in comparison to the traditional delta modulation (DM) scheme while tracking stiff analog input signals, producing a much lower mean square error. The implementation is quite simple as it uses the transmission of 1-bit digital data at a time. On the receiver side, digital-toanalog conversion (DAC) makes use of the same adaptive logic in reconstructing the original input signal. The designed prototype demonstrates its resistance to a wide range of input amplitude and frequency variations. The ADC-DAC design method in this paper is accurate, makes the best use of resources, and is easy to use.

Saha Misra Iti

Papers

Novel design of Address Generator for WiMAX multimode interleaver using FPGA based finite state machine

An innovative FPGA-based ADC/DAC design using 1-bit adaptive-delta modulation