S
Sam Gat-Shang Chu
Researcher at IBM
Publications - 48
Citations - 777
Sam Gat-Shang Chu is an academic researcher from IBM. The author has contributed to research in topics: Register file & Microprocessor. The author has an hindex of 14, co-authored 48 publications receiving 776 citations.
Papers
More filters
Proceedings ArticleDOI
Design of the Power6 Microprocessor
Joshua Friedrich,Bradley McCredie,Norman Karl James,B. Huott,Brian W. Curran,Eric Fluhr,Gaurav Mittal,E. Chan,Y.H. Chan,Donald W. Plass,Sam Gat-Shang Chu,Hung Le,L. Clark,J. Ripley,Scott A. Taylor,Jack DiLullo,M. Lanzerotti +16 more
TL;DR: The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability.
Proceedings ArticleDOI
Design and implementation of the POWER5 microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,James W. Dawson,Paul H. Muench,Larry Powell,Michael Stephen Floyd,Balaram Sinharoy,Mike Lee,Michael Normand Goulet,James Donald Wagoner,Nicole Schwartz,Steve Runyon,Gary Alan Gorman,Phillip J. Restle,Ronald Nick Kalla,Joseph McGill,Steve Dodson +20 more
TL;DR: POWERS offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support.
Proceedings ArticleDOI
The implementation of POWER7 TM : A highly parallel and scalable multi-core high-end server processor
Dieter Wendel,Ronald Nick Kalla,Robert Cargoni,Joachim Clables,Joshua Friedrich,Roland Frech,James Allan Kahle,Balaram Sinharoy,William J. Starke,Scott A. Taylor,S. Weitzel,Sam Gat-Shang Chu,Saiful Islam,Victor Zyuban +13 more
TL;DR: Focusing on speed, the dual-supply ripple-domino SRAM concepts follows the schemes described elsewhere.
Journal ArticleDOI
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor
Dieter Wendel,Ronald Nick Kalla,James D. Warnock,Robert Alan Cargnoni,Sam Gat-Shang Chu,Joachim Gerhard Clabes,Daniel M. Dreps,David A. Hrusecky,Joshua Friedrich,Saiful Islam,J. Kahle,Jentje Leenstra,Gaurav Mittal,Jose Angel Paredes,J. Pille,Phillip J. Restle,Balaram Sinharoy,G Smith,William J. Starke,Scott A. Taylor,J. A. Van Norstrand,S. Weitzel,Phillip G. Williams,Victor Zyuban +23 more
TL;DR: The organization of the design and the features of the processor core are described, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs, including special features for test, debug, and chip frequency tuning.
Patent
Enhanced debug scheme for LBIST
Sam Gat-Shang Chu,Joachim Gerhard Clabes,Michael Normand Goulet,Johnny James LeBlanc,James D. Warnock +4 more
TL;DR: In this paper, a second reference signature is generated based on the masking data from the file unit and a scanning data from a scan string in the chip, and a signature logic connected to the output of masking unit is yet further provided for compressing the second register signature and inputting the compressed second register to the LBIST circuit.