This paper proposes a 2-D investigative model for fully depleted dual-material-double-gate (DMDG) metal–oxide–semiconductor-field-effect-transistor (MOSFET) for surface potential profile. Analyses have been made with several oxide thicknesses, doping concentrations and gate voltages. The temperature effect and the interface charge density effect on the proposed surface potential model have also been reported. The different channel length ratios are also incorporated for this investigation. In this model we have also included the effect of high dielectric constant material like HfO2 and made a comparative study with the influence of different parameters. As anticipated, in DMDG structure the surface potential along the channel shows a step function which suppresses many short channel effects (SCEs). In the result the model shows that to get the same value of surface potential, the oxide thickness using HfO2 will be greater than SiO2. All the results of the analytical model outcomes have been endorsed by technology computer aided design (TCAD) simulation results. Tremendous conformity among them is observed.

Analysis of surface potential for dual-material-double-gate MOSFET based on modeling and simulation

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

In this work, the performance of a Si0.5Ge0.5 sourced dual electrode doping-less Tunnel FET (DEDLTFET) biosensor using dielectric modulation is studied for different cavity length, thickness (Tbio) and charge densities (QF). The use of silicon-germanium (SiGe) based source also shows an improvement in the performance of the charge plasma Tunnel FET because of its enhanced drain current. Biomolecules are introduced inside the cavity region and their impact on the drain current has been investigated to design the biosensor. The sensitivity factor of the biosensor depends upon the drain current obtained which is proportional to the dielectric constant (k) and the charge density of the biomolecules. The proposed biosensor achieves a maximum drain current sensitivity of 7.7 × 108 at a cavity length of 25 nm and 2.7 × 109 at a cavity length of 30 nm. When compared with the conventional TFET biosensors, it is observed that Si0.5Ge0.5 sourced doping-less TFET biosensor provides better drain current sensitivity.

Label Free Detection of Biomolecules Using SiGe Sourced Dual Electrode Doping-Less Dielectrically Modulated Tunnel FET

In this article, a two dimensional (2-D) threshold voltage modeling based gate and channel engineering are developed analytically for Dual Halo Gate Stacked Triple Material Dual Gate Tunnel FET (DH-GS-TM-DG-TFET) with effective surface charge. The model is derived by solving the 2-D Poisson equation in Silicon graded channel region using suitable boundary conditions. The proposed model incorporates the effects of various device parameters such as channel potential, electric field, DIBL, threshold voltage roll-off and drain current. Also, the fringing capacitance characteristics of the proposed DH-GS-TM-DG-TFET demonstrate superior performance over Triple material double gate and Single material double gate TFET structures. It is evident that the proposed device structure DH-GS-TM-DGTFET provides poor outflow current IOFF (10−16A/μm), and remarkable betterment in ON current (10−6A/μm). Moreover, the ION/IOFF ratio is 1010. To validate the robustness of model, the numerical results are compared with those obtained using Sentaurus TCAD.

Influence of Threshold Voltage Performance Analysis on Dual Halo Gate Stacked Triple Material Dual Gate TFET for Ultra Low Power Applications

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents $I_{on}$ and less than 1/10th the off-currents $I_{off}$ of equivalent, equally-sized mosfet s at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low $V_{t}$ Transistors (LVT) and High $V_{t}$ Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4  $\mu$ W power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26  $\mu$ W power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.

An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices

A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A silicon‐based dual‐material double‐gate tunnel field‐effect transistor with optimized performance

In this work, prospects of nanocavity embedded Dual Metal Double Gate Tunnel FET device as a label free biosensor have been analyzed for neutral biomolecule detection A numerical model of the device has been developed in Atlas, Silvaco and device electrical characteristics for the presence of different biomolecules have been observed Based on the device performance, sensing metrics have been indicated Sensitivity of the sensing metrics like tunneling current, threshold voltage, Sub-threshold Slope have been analyzed for the presence of varying biomolecules Additionally, the filling factor of the biomolecules in the cavities has been analyzed It has also been found that dual metal structure provides better sensitivity than the single metal counterpart

Application of nanocavity embedded dual metal double gate TFET in biomolecule detection

In this work, we report the modeling and design of a high-speed Ge-based plasmonic detector coupled with a Metal-Insulator-Metal (MIM) plasmonic majority gate. The detector is designed to distinguish between multiple output levels of the integrated majority gate. Through numerical analyses we predict the proposed plasmonic detector has an intrinsic bandwidth beyond $\text{220 GHz}$ at an applied bias of only $\text{100 mV}$ . An asymmetric Metal-Semiconductor-Metal (MSM) configuration of the plasmonic detector ensures a dark current of a few nA which results in high sensitivity. The high electric field generated by the electrode asymmetry enables effective separation of the photogenerated carriers resulting in high photocurrent even at few mVs of applied bias. The low capacitance of less than $1fF$ arising from the small detector dimensions results in a high RC-limited bandwidth. Moreover, the narrow plasmonic Ge slot of the photodetector provides a short drift path and fast transit time for carriers. Unlike previously reported plasmonic detectors that use noble metals as electrodes, our proposed detector employs Al and Cu to meet CMOS compatibility requirements and thus can be a potential candidate for high-speed computational systems in industry-level applications. Additionally, the findings presented in the article will be helpful for the future realization of an integrated plasmonic system.

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Samantha Lubaba Noor

Papers

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A silicon‐based dual‐material double‐gate tunnel field‐effect transistor with optimized performance

Application of nanocavity embedded dual metal double gate TFET in biomolecule detection

Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates