Sameer Singh

Bio: Sameer Singh is an academic researcher from Cadence Design Systems. The author has contributed to research in topics: Intermodulation & Elliptic filter. The author has an hindex of 1, co-authored 2 publications receiving 22 citations. Previous affiliations of Sameer Singh include Indian Institutes of Technology.

A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps

Abstract: A low-distortion active filter is realized using current-efficient feedforward-compensated operational amplifiers in the integrators and feedforward current injection in the summing amplifier. A third-order elliptic low-pass filter with two possible bandwidth settings of 17 and 8.5 MHz consumes 1.8 mW from a 1.8-V supply and occupies 0.17 mm2 in a 0.18- μm CMOS process. The measured maximum signal-to-noise and distortion ratios at the two bandwidth settings are 50.5 and 52.5 dB, respectively. The corresponding third-order intermodulation intercept points (IIP3) are +28.2 and +30.8 dBm. Automatic tuning is used at the startup to counter process variations and set the bandwidth accurately.

A 23fJ/conv-step 12b 290MS/s time interleaved pipelined SAR ADC

Abstract: This paper describes the techniques used in the design of a 12-bit 290MS/s two stage time interleaved (TI) SAR ADC that minimizes the sampling skew and gain mismatches between multiple high resolution cores without the need for background digital calibration. A timing scheme which allows sharing of a single reference buffer and optimal distribution of conversion time among MSB and LSB bits is used. Further optimization in power is achieved by use of a process, voltage and temperature (PVT) invariant asynchronous timing loop that avoids pessimistic margins and simplifies design. The ADC is implemented in TSMC 28HPM process and achieves high input frequency figure of merit (FoM) of 23fJ/conv-step. Its high frequency Schreier FoM is 165.3dB, which is the highest reported number at this sampling range. The architecture is extended towards implementation of a 12-bit 460MS/s ADC, where two such instances are interleaved to achieve FoM of 30fJ/conv-step and greater than 70dB SFDR.

A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS

Abstract: An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of $LC$ or transmission line-based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter’s order while keeping the bandwidth constant and fine tuning is implemented by changing the filter’s bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13 $\mu \text{m}$ CMOS process demonstrates a delay tuning range of 250 ps–1.7-ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a DBW of 3.4 and a delay per unit area of 5.8 $\mathrm {ns/mm^{2}}$ . The filter has a worst case noise figure of 23 dB, and −40 dB intermodulation (IM3) distortion for 37 mVppd inputs. The chip occupies an active area of 0.6 mm2, and dissipates 112 mW–364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced $\mathrm {\lambda _{fmax}}/2$ apart shows ±90° beam steering off broadside.

FEATS: Framework for Explorative Analog Topology Synthesis

Abstract: This paper proposes a new methodology for automated analog circuit synthesis, aiming to address the challenges known from other analog synthesis approaches: unsatisfactory time predictability due to stochastic-driven circuit generation methods, the dereliction of the creative part during the design process, and the inflexibility leading to synthesis tools, which mostly only handle just one circuit class. This contribution presents the underlying concepts and ideas to provide the predictability, flexibility, and creative freedom in order to elevate analog circuit design to the next step. A circuit generation algorithm is presented, which allows a full design-space exploration. Furthermore, an isomorphism algorithm is developed, which reduces a given set of circuits to its unique being one of the first methodologies addressing this issue. Thus, the algorithm handles vast amounts of circuits in a very efficient manner. The results demonstrate the claimed feasibility and applicability of the synthesis framework in general and in the context of system design.

A Compensation Technique for Two-Stage Differential OTAs

Abstract: In this brief, a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3-dB bandwidth, the unity gain frequency, and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole. The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values, which makes it attractive for low-power applications with low area overhead.

A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection

Abstract: This article presents a fully differential (FD) low-voltage (LV) fourth-order Butterworth active- RC low-pass filter (LPF) with a maximum cutoff frequency $(f_{o})$ of 160 MHz, $f_{o}$ programmability, and adaptive power The proposed filter targets communication systems requiring high and reconfigurable $f_{o}$ at supply voltages $(V_{\mathrm {DD}}s)$ of 06 V The filter is implemented with an active- RC topology, a programmable $f_{o}$ between four steps, 20/40/80/160 MHz, and a $f_{o}$ fine-tuning option after fabrication via capacitor banks A compact LV FD amplifier with feedforward gain-boosting implementation is used to meet the stringent filter’s performance The novel amplifier achieves an open loop gain of 66 dB and a maximum unity-gain frequency (UGF) of 759 MHz with $V_{\mathrm {DD}} = 06$ V and 527 mW of power dissipation Using the proposed amplifier, the filter achieves the highest $f_{o}$ reported in the literature for LV active- RC implementations and 40% power reduction over similar high- $f_{o}$ LV filters The filter was fabricated in a CMOS 130-nm technology; it has a THD = 507 dB, signal-to-noise and distortion (SNDR) = 4537 dB, $P_{\mathrm {1dB}} = 426$ dBm and 520- $\mu \text{V}$ RMS integrated noise over the filter’s bandwidth (BW), while consuming 238 mA from a 06-V supply for $f_{o} = 160$ MHz