Showing papers by "Samit K. Ray published in 2006"

The effect of substrate temperature on the properties of ITO thin films for OLED applications

Abstract: Indium tin oxide (ITO) thin films have been deposited by rf magnetron sputtering on glass substrates at different substrate temperatures. The structural, electrical and optical properties of these films have been investigated to obtain optimum values for resistivity, optical transmittance and surface smoothness. The film deposited at a substrate temperature of 300 °C shows good conductivity, optical transmittance, crystallinity and surface smoothness. These ITO films were used to fabricate organic light emitting diodes (OLEDs). The dc current–voltage (I–V) studies on ITO/PEDOT:PSS/MEH-PPV/Al test structures show better rectifying behaviour on a smoother ITO substrate.

High-k gate oxide for silicon heterostructure MOSFET devices

Abstract: Very exciting and promising results from recent developments in group-IV alloy heterostructures (viz., SiGe, SiGeC, SiC, GeC and strained-Si) have led to the belief that SiGe-based devices will open up an entirely new dimension to the future of VLSI/ULSI technology. The growth of ultrathin dielectric films on a strained group-IV alloy layer is a challenging task. As metal-oxide-semiconductor devices are being aggressively scaled down, high permittivity dielectrics are being widely investigated as alternative gate insulating layers in advanced MOS devices. The present paper reviews the recent results of different gate and high-k dielectrics on group-IV alloy layers for scaled CMOS devices, high-mobility pure-Ge channel devices and nanocrystal floating gate memories.

Design, growth, fabrication, and characterization of InAs/GaAs 1.3 μm quantum dot broadband superluminescent light emitting diode

Abstract: In this paper we discuss a technique for broadening the emission and gain spectra of 1.3μm quantum dot superluminescent light emitting diodes (SLEDs). By incorporating different amounts of indium in different wells of a multi-dot-in-well stack we are able to tailor the emission and gain spectra of the devices. This technique allows us to overlap the ground state of one dot-in-well (DWELL) with the excited state of another to achieve broader and flatter emission spectra compared to a SLED design comprising DWELL layers of constant indium composition. Due to the low internal loss of these structures, this broadening is achieved without a significant reduction in the output power of the devices.

Electrical properties of ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructures

Abstract: Ultrathin HfO2 gate dielectrics have been deposited on strained Si0.69Ge0.3C0.01 layers by rf magnetron sputtering. The polycrystalline HfO2 film with a physical thickness of ∼6.5 nm and an amorphous interfacial layer with a physical thickness of ∼2.5 nm have been observed by high resolution transmission electron microscopy (HRTEM). The electrical properties have been studied using metal-oxide-semiconductor (MOS) structures. The fabricated MOS capacitors on Si0.69 Ge0.3C0.01 show an equivalent oxide thickness (EOT) of 2.9 nm, with a low leakage current density of ∼4.5 × 10 − 7 A/cm2 at a gate voltage of –1.0 V. The fixed oxide charge and interface state densities are calculated to be 1.9 × 1012 cm− 2 and 3.3 × 10 11 cm− 2eV−1, respectively. The temperature dependent gate leakage characteristics has been studied to establish the current transport mechanism in high-k HfO2 gate dielectric to be Poole–Frenkel one. An improvement in electrical properties of HfO2 gate dielectrics has been observed after post deposition annealing in O2 and N2 environments.

Characteristics of ZrO2 gate dielectrics on O2- and N2O-plasma treated partially strain-compensated Si0.69Ge0.3C0.01 layers

Abstract: The characteristics of ZrO2 gate dielectric along with the interfacial layer on O2- and N2O-plasma treated partially strain-compensated Si0.69Ge0.3C0.01∕Si heterostructures have been investigated using spectroscopic and electrical measurements. Time-of-flight secondary ion mass spectroscopy and x-ray photoelectron spectroscopy analyses show the formation of an oxygen or nitrogen rich Zr-germanosilicate interfacial layer between the deposited ZrO2 and SiGeC films. The electrical and charge trapping properties under a constant current stressing have been studied using a metal-oxide-semiconductor structure. The N2O-plasma treated SiGeC film has a higher effective dielectric constant (k∼14) than that of the O2-plasma treated (k∼12) films. The equivalent areal densities of charge defects, Neq (cm−2), are found to be ∼1.8×1012 and ∼6×1011cm−2 for O2- and N2O-plasma treated films, respectively. Considerably less trapped charges in the N2O-treated gate dielectric stack under constant current stressing make it hig...

MBE Growth of High Power Quantum Dot Superluminescent LEDs

Abstract: In this paper we demonstrate record high output powers for 1.3μm quantum dot superluminescent diodes through an improvement in growth conditions. Such devices exhibit 40mW CW output powers with emission bandwidths of 21nm. Introduction: Superluminescent LEDs (SLEDs) are of growing interest for applications requiring a high output power and broad emission band. Application of significant interest is Optical Coherence Tomography, which requires high output power (>10mW) for millimetre range penetration depth [1]. Operating wavelengths of 1050 nm and 1300 nm are required corresponding to the minimum in dispersion and loss for skin tissue, respectively. The growth of high quality, long wavelength QD structures is technologically difficult as InAs QDs are typically grown at a low temperature, and in order to achieve long wavelengths low temperature InGaAs barrier layers capping the QDs are required (DWELL, dot –in-well). Previously we reported low threshold current density, 1.31μm InAs/GaAs QD lasers incorporating a high temperature growth step for GaAs barrier layers separating the DWELLs [2]. In this paper we present improved growth parameters for high power QD SLEDs, where the thickness of the low temperature GaAs following DWELL deposition is reduced from 15 nm to 2nm in thickness. We demonstrate a ~4 fold increase in SLED CW output power leading to 40mW output powers with a spectral linewidth of 21nm at 1A drive current. This correlates with a concomitant reduction in the threshold current density (Jth) of laser diodes, and a reduction in reverse leakage current and increase in breakdown voltage for mesa diodes. Device Growth and Fabrication: For both of our devices optical confinement was achieved using 1500nm Al0.4Ga0.6As cladding layers. The DWELL layer consisted of 3.0 monolayers (MLs) of InAs grown on 2nm of In0.15Ga0.85As covered by 6nm of In0.15Ga0.85As. Seven InAs/InGaAs DWELLs were separated by 50nm GaAs barriers and embedded between 150nm separate confinement hetero-structure GaAs layers. The DWELL layers were delta p-doped with 12 Be acceptors per QD. To reduce the detrimental effects associated with the low growth temperature we utilised two indium cells [3]. Areal dot density of 3.5x10cm per layer was measured by atomic force microscopy on uncapped structures. A VG Semicon V90H molecular beam epitaxy system was used to grow the SLED structures on a Si doped GaAs (110) substrate. We investigated two samples, for both structures the growth temperatures were Tgrowth= 620°C for the AlGaAs and Tgrowth=510°C for the In containing layers. The samples differed only in the temperature ramp of the barrier layers between DWELL layers. One structure incorporated our standard low temperature GaAs barrier layer (SLTBL) utilised for 1.3 μm laser structures (15nm Tgrowth=510°C, 35nm Tgrowth=620°C), and the other with a thin low temperature barrier layer (TLTBL) (2nm Tgrowth=510°C, 48nm Tgrowth=620°C). The SLED ridges were tilted by 8 from the normal to the as-cleaved facet. The results shown here are for SLED ridges, which are 15μm wide. CW and pulsed measurements showed similar trends, though CW results are described here. Result and Discussion: Figure 1 shows the room temperature CW current-power response for SLTBL and a TLTBL SLED devices of cavity length 8mm. At all current densities the plot shows ~4 fold increase in output power for the TLBTL SLED compared to the SLTBL SLED at room temperature. The “threshold” current for superluminescence is observed to be smaller for the TLTBL sample than the SLTBL device. For an injection of 1Amp CW current the TLTBL SLED gives an output power over 40mW and a spectral bandwidth of 21nm. Figure 2 shows the leakage current as a function of reverse bias voltage plot for mesa diodes of 50μm radius. At all reverse biases the leakage current is lower for the TLTBL compared to that Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -276B-6-4 pp. 276-277