Samuel Menard

Bio: Samuel Menard is an academic researcher from François Rabelais University. The author has contributed to research in topics: Substrate (electronics) & Porous silicon. The author has an hindex of 2, co-authored 4 publications receiving 20 citations.

High-voltage vertical power component

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Vertical power component

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

Dielectric behavior of porous silicon grown from p-type substrates

Abstract: Dielectric properties of porous silicon (PS) grown from P-type substrates are analyzed in details in order to assess its integration in power device peripheries. The study focuses on three different substrate resistivities in order to access to a larger panel of porosities (P) and PS morphologies. PS resistivity (ρ PS ) and dielectric constant (e PS ) are reported as a function of P. At room temperature, e PS values lower than 4 and ρ PS higher than 1e9 Ω.cm can be reached by increasing P up to 70%. However, some deviations are observed suggesting a more complex behavior where the PS morphology should be involved.

Vertical semiconductor power component capable of withstanding high voltage

Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.

Dielectric properties of porous silicon for use as a substrate for the on-chip integration of millimeter-wave devices in the frequency range 140 to 210 GHz.

Abstract: In this work, the dielectric properties of porous Si for its use as a local substrate material for the integration on the Si wafer of millimeter-wave devices were investigated in the frequency range 140 to 210 GHz. Broadband electrical characterization of coplanar waveguide transmission lines (CPW TLines), formed on the porous Si layer, was used in this respect. It was shown that the dielectric parameters of porous Si (dielectric permittivity and loss tangent) in the above frequency range have values similar to those obtained at lower frequencies (1 to 40 GHz). More specifically, for the samples used, the obtained values were approximately 3.12 ± 0.05 and 0.023 ± 0.005, respectively. Finally, a comparison was made between the performance of the CPW TLines on a 150-μm-thick porous Si layer and on three other radiofrequency (RF) substrates, namely, on trap-rich high-resistivity Si (trap-rich HR Si), on a standard complementary metal-oxide-semiconductor (CMOS) Si wafer (p-type, resistivity 1 to 10 Ω.cm) and on quartz. 84.40.-x; 77.22.Ch; 81.05.Rm

Integrated Circuit Device Having Through-Silicon-Via Structure and Method of Manufacturing the Same

Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.

Vertical power component

Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.

Investigation of Porous Silicon-Based Edge Termination for Planar-Type TRIAC

Abstract: This paper aims to investigate a porous silicon (PS)-based edge termination for planar type ac switch. TRIAC device prototypes, specifically dedicated to evaluate blocking performances, are fabricated by integrating electrochemical etching in device processing. A mixed porous morphology containing micro-, meso-, and macropores is obtained in a p-Type through-wafer-diffused via after anodization. The fabricated prototypes show PS-dependent blocking capabilities. The possible impacts of the anodization conditions and the physical features of PS on the electrical characteristics are discussed in detail. Low leakage currents ( $ ) have been demonstrated up to several hundred voltages for both bias polarities. The forward blocking voltage decreases with increasing PS thickness, while an opposite trend is observed for the reverse blocking voltage. This paper confirms the interest of PS as a potential insulating material for power device manufacture.

Integrated circuit device having through-silicon-via structure

Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.