Sang-Ho Kim

Bio: Sang-Ho Kim is an academic researcher from Samsung. The author has contributed to research in topics: Low-dropout regulator & Dropout voltage. The author has an hindex of 9, co-authored 25 publications receiving 285 citations.

A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor

Abstract: This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm2. The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

Abstract: A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

8.3 A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors

Abstract: A modern mobile application processor (AP) requires a variety of power voltage levels, which increases the number of external capacitors around the mobile AP. This is because the supply PCB routes from the power management IC (PMIC) to the AP have parasitic inductors. The parasitic inductors introduce ripples on power voltage lines. Therefore, external capacitors are required on the PCB routes between the PMIC and the mobile AP. To reduce the number of external capacitors, one power voltage level from the PMIC is converted into a variety of power voltage levels inside the mobile AP. This both reduces external capacitors as well as the number of power pins on the mobile AP and simplifies PCB routes. For such reasons, integrated low-dropout regulators (LDOs) are preferred in mobile APs.

Dual-Path Three-Level Buck Converter With Loop-Free Autocalibration for Flying Capacitor Self-Balancing

Abstract: This letter proposes a loop-free autocalibration technique for self-balancing of flying capacitors in a three-level dc–dc buck converter. The proposed converter utilizes a dual-path power stage with balancing switches that adaptively short flying capacitors at de-energizing phases. Thus, the dual-path three-level converter ensures that flying capacitor voltages are self-balanced at half the input voltage without using additional feedback calibration loops, leading to robust operation and competitive efficiencies. The prototype was fabricated in the 0.13- μ m CMOS BCD process and adopted two flying capacitors of 4.7 μ F each and an inductor of 10 μ H with a dc resistance of 128 mΩ. When an 8-V input was converted to a 3-V output voltage with a load current of 400 mA, the measured efficiency was 88.6% at 800 kHz switching while flying capacitors are automatically balanced.

System and method for performing transmission and reception operations based on broadcast/communication convergence

Abstract: A system for performing transmission and reception operations based on broadcast/communication convergence. A transmitter adapted for the broadcast/communication convergence converts input broadcast data into a parallel format, inserts port identification (Port ID) information into each of the broadcast data converted into the parallel format and input communication data, multiplexes the broadcast data and the communication data, and transmits a broadcast/communication convergence signal based on a result of the multiplexing through a single transmission channel. A receiver adapted for the broadcast/communication convergence demultiplexes the broadcast/communication convergence signal using the Port ID information to be separated into the broadcast data and the communication data when the broadcast/communication convergence signal is received, and outputs data to a corresponding destination.

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

Abstract: An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

Electronic television program guide schedule system and method with scan feature

Abstract: An electronic program schedule system which utilizes a receiver for receiving broadcast, satellite or cablecast television programs for a plurality of television channels and a tuner for tuning a television receiver to a selected one of the plurality of channels. A data processor receives and stores in a memory television program schedule information for a plurality of television programs to appear on the plurality of television channels. A user control apparatus, such as a remote controller, is utilized by a viewer to choose user control commands and transmit signals in response to the data processor which receives the signals in response to user control commands. A television receiver is used to display the television programs and television program schedule information. A video display generator receives video control commands from the data processor and program schedule information from the memory and displays a portion of the program schedule information in overlaying relationship with a television program appearing on a television channel in at least one mode of operation of the television programming guide. The data processor controls the video display generator with video control commands, issued in response to the user control commands, to display program schedule information for any chosen one of the plurality of television programs in overlaying relationship with at least one television program then appearing on any chosen one of the plurality of channels on the television receiver. The system includes a scan feature to permit the user to scan program schedule listings for multiple programs in any of the operational modes of the system with the issuance of a single user control command.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

Abstract: This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor

Abstract: This paper proposes a coarse-fine dual-loop architecture for the digital low drop-out (LDO) regulators with fast transient response and more than 200-mA load capacity. In the proposed scheme, the output voltage is coregulated by two loops, namely, the coarse loop and the fine loop. The coarse loop adopts a fast current-mirror flash analog to digital converter and supplies high output current to enhance the transient performance, while the fine loop delivers low output current and helps reduce the voltage ripples and improve the regulation accuracies. Besides, a digital controller is implemented to prevent contentions between the two loops. Fabricated in a 28-nm Samsung CMOS process, the proposed digital LDO achieves maximum load up to 200 mA when the input and the output voltages are 1.1 and 0.9 V, respectively, with a chip area of 0.021 mm2. The measured output voltage drop of around 120 mV is observed for a load step of 180 mA.

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique

Abstract: The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.