Sangeet Saha

TL;DR: Methods for scheduling periodic hard real-time dynamic task sets on fully and partially reconfigurable field-programmable gate arrays (FPGAs) are presented and Experimental results reveal that the proposed algorithms are able to achieve high resource utilization with low task rejection rates over a variety of simulation scenarios.

TL;DR: This work presents a co-scheduling framework for the combined execution of such periodic and aperiodic real-time tasks on fully and run-time partially reconfigurable platforms and reveals that the proposed scheduling strategies are able to achieve high resource utilization with low task rejection rates over various simulation scenarios.

TL;DR: This work tackles real-life traffic load recognition problem on System-On-a-Programmable-Chip (SOPC) platform and coin it as MAT-CNN-SOPCs, which uses an intelligent retraining mechanism of the CNN with known environments, which is capable of enhancing the efficacy of the approach by 2.44x.

TL;DR: In this article, the authors tackled real-life traffic load recognition problem on System-On-a-Programmable-Chip (SOPC) platform and coined it as MAT-CNN-SOC, which uses an intelligent re-training mechanism of the CNN with known environments.

TL;DR: This paper proposes a hybrid approach of resource mapping technique on DVFS enabled MPSoC, which is suitable for IDE integration due to the reduced design points in the methodology resulting in significant reduction in profiling time.