Sanghamitra Debnath

Bio: Sanghamitra Debnath is an academic researcher from North Eastern Regional Institute of Science and Technology. The author has contributed to research in topics: Steganography & Steganography tools. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

A review on hardware implementation of steganography

Abstract: Steganography deals with embedding secret data within inoffensive looking objects called “Cover Objects.” To accomplish this, intensive computations are required to be performed. Modern day steganography can be implemented using both software and hardware for the purpose of obscurity based security or Kerckhoffs's principle based Shannon's maxim. The algorithm used in both the implementations may be in spatial or transform domain. Moreover, hardware implementations may be done via a lot of variants among which FPGA (Field Gate Programmable Array) based implementations are most user-friendly and easy to implement and reconfigure. Hardware implementation speeds up the embedding process where as transform domain increases robustness. But the complexity of transform domain is huge compared to the spatial domain. So the simple and fast FPGA-based spatial domain real time hardware implementation of steganography becomes an important field to explore. This paper gives an overview of the hardware platforms and discusses several works done in implementing steganographic algorithms in hardware mainly in the FPGA-based spatial domain.

Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

Abstract: Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

Design of an Efficient Steganography Model using Lifting based DWT and Modified-LSB Method on FPGA

Abstract: The data transmission with information hiding is a challenging task in today world. To protect the secret data or image from attackers, the steganography techniques are essential. The steganography is a process of hiding the information from one channel to another in data communication. In this research work, Design of an Efficient Steganography Model using Lifting Based DWT and Modified-LSB Method on FPGA is proposed. The stegano module includes DWT (Discrete Wavelet Transformation) with lifting scheme for the cover image and encryption with Bit mapping for a secret image, an embedded module using Modified Least Significant Bit (MLSB) Method, and Inverse DWT to generate the stegano image. The recovery module includes DWT, decoding module with pixel extraction and bit retrievals, and decryption to generate the recovered secret image. The steganography model is designed using Verilog-HDL on Xilinx platform and implemented with Artix-7 Field Programmable Gate Array (FPGA). The hardware resource constraints like Area, time, and power utilization of the proposed model results are tabulated. The performance analysis of the work is evaluated using Peak Signal to Noise Ratio (PSNR) and Mean Square Error (MSE) Ratio for a different cover and secret images with better quality. The proposed steganography model operates at high speed, which improves communication performance.