International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high-K-metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics. This Perspective examines the use of ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models, arguing that the devices will be a key component in the development of data-centric computing.

The future of ferroelectric field-effect transistor technology

We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

Demonstration of L-Shaped Tunnel Field-Effect Transistors

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf 0.8 Zr 0.2 O 2 , High Endurance and Breakdown Recovery

In this work, novel L-shaped tunneling field-effect transistors (TFETs) have been proposed. The proposed L-shaped TFETs feature higher on-current (Ion) and lower subthreshold swing (SS) than conventional TFETs. It is because L-shaped TFETs have large cross-sectional area of band-to-band tunneling junction which is perpendicular to the channel direction and their tunneling barrier width (Wt) is defined by the length of an intrinsic silicon region. As the devices are based on the Si without any other material, it can be fabricated with well-established Si process technology. In addition, it can moderate some issues come from scaling down and enlarging tunneling area due to its mesa structure. Simulation results have confirmed the superiority of L-shaped TFETs over conventional TFETs. Additionally, the effect of some device parameters on device performance has been investigated for the clear verification of its operation mechanism and the optimization.

https://iopscience.iop.org/article/10.1143/JJAP.51.06FE09/pdf

Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors

This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and ${10}^{ {4}}~{ \mathrm{\scriptstyle ON}}/{ \mathrm{\scriptstyle OFF}}$ current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ${I}_{D}$ regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

Environment-adaptable photonic-electronic-coupled devices can help overcome major challenges related to the extraction of highly specific angular information, such as human visual perception. However, a true implementation of such a device has rarely been investigated thus far. Herein, we provide an approach and demonstrate a proof-of-concept solid-state semiconductor-based highly transparent, optical-electrical-coupled, self-adaptive angular visual perception system that can fulfill the versatile criteria of the human vision system. Specifically, all of the primitive functions of visual perception, such as broad angular sensing, processing, and manifold memory storage, are demonstrated and comodulated using optical and electric pulses. This development represents an essential step forward in the fabrication of an environment-adaptable artificial angular perception framework with deep implications in the fields of optoelectronics, artificial eyes, and memory storage applications.

Sangwan Kim

Papers

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Self-Aligned, Gate Last, FDSOI, Ferroelectric Gate Memory Device With 5.5-nm Hf 0.8 Zr 0.2 O 2 , High Endurance and Breakdown Recovery

Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

Environment-Adaptable Photonic–Electronic-Coupled Neuromorphic Angular Visual System