This paper presents a complete 50–64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.

A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture [1-3]. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.

3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a pre-cursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15-22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm × 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm × 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.

A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE

Scale-out workloads are characterized by in-memory datasets, and consequently massive memory footprints. Due to the abundance of request-level parallelism found in these workloads, recent research advocates for manycore architectures to maximize throughput while maintaining quality of service. On-die stacked DRAM caches have been proposed to provide the required bandwidth for manycore servers through caching of secondary data working sets. However, the disparity between provided capacity and hot dataset working set sizes — resulting from power-law dataset access distributions — precludes their effective deployment in servers, calling for high-capacity cache architectures. In this work, we find that while emerging high-bandwidth memory technology falls short of providing enough capacity to serve as system memory, it is a great substrate for high-capacity caches. We also find the long cache residency periods enabled by high-capacity caches uncover significant spatial locality across objects. Based on our findings, we introduce Scale-Out Cache (soCache) — a distributed cache composed of multiple high-bandwidth memory modules. Each soCache module uses a page-based organization that optimizes for spatial locality while minimizing tag storage requirements. By storing the tags in the logic die (in SRAM) of the high-bandwidth memory modules, soCache avoids the prohibitive complexity of in-DRAM metadata in state-of-the-art DRAM caches. In 14nm technology, soCache reduces system energy by 1.4-4.4x and improves throughput by 28-44% over state-of-the-art memory systems.

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An Effective DRAM Cache Architecture for Scale-Out Servers

The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10–12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2].

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

As the processing power and clock rate of CPUs and GPUs increase, there is a need for increased I/O bandwidth to enable chip-to-chip communication. I/O pin limitations demand faster links at low power to enable integration of high chip-to-chip bandwidth. However, the channel losses and impedance discontinuities increase at high data rates making it difficult to equalize the channel at low power. In this work, we target reliable, differential, bi-directional links at 20 Gb/s over 6” FR4 PCB trace and flip-chip packages with a total loss budget of 20 dB at Nyquist. In a half-duplex link, one TX and RX are connected on each side and the link direction can be turned around by the controller. A link-turnaround latency of <;10 ns is achieved by placing several key circuits on standby when not in use and by designing fast bias circuits. When fast turnaround is not required, the circuits not in use are powered down permanently and the link is reduced to the simplex case. The top-level transceiver architecture is shown. An LC-VCO-based PLL oscillates at 20 GHz and generates quadrature I/Q clocks at 10 GHz. Both TX and RX use a half-rate architecture to optimize power. The clocks are distributed through an on-chip transmission line to 16 I/O lanes arranged in 2 rows. The links are capable of data rates as low as 14 Gb/s to save power when full bandwidth is not required.

Sanjeev Maheswari

Papers

26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS