Day by day, all the research communities have been focusing on digital image retrieval due to more internet and social media uses. In this paper, a U-Net-based neural network is proposed for the segmentation process and Haar DWT and lifting wavelet schemes are used for feature extraction in content-based image retrieval (CBIR). Haar wavelet is preferred as it is easy to understand, very simple to compute, and the fastest. The U-Net-based neural network (CNN) gives more accurate results than the existing methodology because deep learning techniques extract low-level and high-level features from the input image. For the evaluation process, two benchmark datasets are used, and the accuracy of the proposed method is 93.01% and 88.39% on Corel 1K and Corel 5K. U-Net is used for the segmentation purpose, and it reduces the dimension of the feature vector and feature extraction time by 5 seconds compared to the existing methods. According to the performance analysis, the proposed work has proven that U-Net improves image retrieval performance in terms of accuracy, precision, and recall on both the benchmark datasets.

/pdf/object-based-image-retrieval-using-the-u-net-based-neural-15q3r5uaov.pdf

Object-Based Image Retrieval Using the U-Net-Based Neural Network.

: The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

https://www.techscience.com/cmc/v71n2/45851/pdf

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

In computer vision and medical image processing, object recognition is the primary concern today. Humans require only a few milliseconds for object recognition and visual stimulation. This led to the development of a computer-specific pattern recognition method in this study for identifying objects in medical images such as brain tumors. Initially, an adaptive median filter is used to remove the noise from MRI images. Thereafter, the contrast image enhancement technique is used to improve the quality of the image. To evaluate the wireframe model, the cellular logic array processing (CLAP)-based algorithm is then applied to images. The basic patterns of three-dimensional (3D) images are then identified from the input image by scanning the whole image. The frequency of these patterns is also used for object classification. A deep neural network is then utilized for the classification of brain tumor. In the proposed model, the syntactic pattern recognition technique is used to find the feature vector and 3D AlexNet is used for brain tumor classification. To evaluate the performance of the proposed work, three benchmark brain tumor datasets are used, i.e., Figshare, Brain MRI Kaggle, and Medical MRI datasets and BraTS 2019 dataset. The comparative analyses reveal that the proposed brain tumor classification model achieves significantly better performance than the existing models.

/pdf/efficient-3d-alexnet-architecture-for-object-recognition-1rodau0k.pdf

Efficient 3D AlexNet Architecture for Object Recognition Using Syntactic Patterns from Medical Images

Khasi is a language that belongs to the Mon-Khmer language of the Austroasiatic group. Khasi language is spoken by the indigenous people of the state of Meghalaya in India. This paper presents a work on Part-of-speech (POS) tagging for the Khasi language by using the Conditional Random Field (CRF) method. The main significance of this work, is to experiment with the CRF model for PoS tagging in the Khasi language. This method produces a reliable agreement on the features of the language. POS tagging for Khasi is essential for creating lemmatizers which are used to lessen a word to its root structure and the POS corpus or dataset can be used in other NLP applications. In this research work, we have designed a tag set and POS tagging corpus. Khasi does not have any standard POS corpus. Therefore, we have to build a Khasi corpus that consists of around 71,000 tokens. After feeding the Khasi corpus to the CRF model for learning, the system yields a testing accuracy of 92.12% and an F1-score of 0.91. The result is compared with few other state-of-art techniques. It is observed that our approach produces promising results in comparison with other techniques. In future, we will increase the size of the Khasi POS corpus.

Part-of-speech (POS) tagging using conditional random field (CRF) model for Khasi corpora

Reliable networking is an important factor in Ethernet ring mesh networks (ERMs) with ITU-T G.8032 Ethernet ring protection recommendation or with the IEC 62439-3 high-availability seamless redundancy protocol. However, there are two major challenges for this purpose: (1) Hitherto, irregular topologies are used in ERMs that it causes difficulty in analyzing and improving reliability. (2) A topology is appropriate for practical implementation, if it is low cost, simple to implement, and simple to develop for large scale-systems (i.e. scalable). However, irregular topologies are extremely difficult to implement and develop. To deal with these challenges, this paper introduces two regular topologies called chordal ring and k-cube networks, for the first time in the area of ERMs. In addition, the proposed topologies are carefully analyzed in terms of reliability. These analyzes prove that the proposed regular topologies outperform existing irregular multiple-ring networks namely shared link, shared node, complex shared link, redundant link, and 3-connected network.

Reliable networking in Ethernet ring mesh networks using regular topologies

Comparative Design and Analysis of Mesh, Torus and Ring NoC☆

Network on chip (NoC) architecture is the promising solution over the limitations of bus-based system. The on-chip communication is addressed by several NoC topological structures and guarantees reliable, fast, and scalable design. The paper addresses the design of fat NoC tree topology that can process the intercommunication from top to root nodes. The tree NoC is indirect topology in which the routers are not dependent on the number of ports. The design is developed in Xilinx ISE 14.2 software with the help of VHDL language, and the design is targeted on Virtex-5 FPGA. The hardware parameters and timing values are estimated to support the functionality of the design.

Fat Tree NoC Design and Synthesis

The research article proposed the 3D mesh topological network on chip (NoC) and its hardware chip implementation. 3D NoC improves the performance of on-chip communication network because the connection of the switches and their length to connecting links is shorter and the data can be switched across the on-chip communication network with the help of less number of switches. The cluster size of the designed 3D mesh NoC is chosen as 4 × 4 × 4. The addressing scheme and intercommunication among nodes is verified in the scalable design. The proposed 3D mesh NoC is designed with the help of VHDL programming language, simulated in ModelSim 10.1 and synthesized in Xilinx ISE 14.2 as software tools. The communication is realized based on look ahead XYZ routing algorithm. The targeted FPGA is Virtex-5 and hardware and timing parameters are also analyzed in the same design.

Scalable Design and Synthesis of 3D Mesh Network on Chip

In the information age, the huge amount of data and information are exchanged which requires fast and efficient searching mechanisms for effective use of this information. There are various sequential searching algorithms to search an element in an unsorted array or sorted array of elements. A number of researchers have explored methods for improving the efficiency and speedup of search using parallel hardware, for eg. A 2-D Mesh of Processors can be used to solve various searching problems in O(n1/2) time regardless of any assumption about wire delay. We proposed an algorithm for searching on Hypercube Interconnection network that solves the basic query problem, namely given an integer x, it is required to search a file of records on the s field for x. Proposed algorithm produces a yes or no answer to such a query in O(log n) time.

An efficient parallel searching algorithm on Hypercube Interconnection network

Power control and soft handoff are the two essential techniques for effectively increasing the spectrum efficiency in a CDMA based system. Soft handoff (SHO) handles the mobility of mobile terminals while power control aims at minimizing the total interference in a CDMA system. During SHO power control procedure is more complicated since at least two base stations are involved. Soft handoff and power control exhibit a close relationship in CDMA based systems. This paper presents an overview and critical analysis of published work in power control during soft handoff in the downlink direction of 3G WCDMA cellular networks and discusses current trends therein.

http://ieeexplore.ieee.org/iel5/6415466/6449780/06449889.pdf

Sanjeev Sharma

Papers

Comparative Design and Analysis of Mesh, Torus and Ring NoC☆

Fat Tree NoC Design and Synthesis

Scalable Design and Synthesis of 3D Mesh Network on Chip

An efficient parallel searching algorithm on Hypercube Interconnection network

Trends in power control during soft handoff in downlink direction of 3G WCDMA cellular networks