Santonu Sarkar

Bio: Santonu Sarkar is an academic researcher from Birla Institute of Technology and Science. The author has contributed to research in topics: Software as a service & Software system. The author has an hindex of 22, co-authored 125 publications receiving 2048 citations. Previous affiliations of Santonu Sarkar include Jadavpur University & Accenture.

Measurements-Based Analysis of Workload-Error Relationship in a Production SaaS Cloud

Abstract: This article consists of a collection of slides from the author's PowerPoint conference presentation. A procedure and a statistical model to measure the risk of error when processing a workload X is proposed. It is concluded that architecting hazard-aware load balancer for Cloud SaaS can be promising.

Fast Fourier transform using linear tagged systolic array

Abstract: A systematic methodology for design of systolic arrays from a set of nonlinear and nonuniform recurrence equations is discussed. A novel architectural idea, which is name tagged systolic array, is introduced. A tagged systolic array uses tags for data routing among processing elements. The design methodology described broadens the class of algorithms amenable for tagged systolic array implementation. The design methodology is illustrated by deriving a tagged systolic array for the fast Fourier transform. >

SamaTulyata: An Efficient Path Based Equivalence Checking Tool

Abstract: An application program can go through significant optimizing and parallelizing transformations, both automated and human guided, before being mapped to an architecture Formal verification of these transformations is crucial to ensure that they preserve the original behavioural specification PRES+ model (Petri net based Representation of Embedded Systems) encompassing data processing is used to model parallel behaviours more vividly This paper presents a translation validation tool for verifying optimizing and parallelizing code transformations by checking equivalence between two PRES+ models, one representing the source code and the other representing its optimized and (or) parallelized version

Design Assistant Tool

Abstract: A design assistant tool may automatically generate a functional design diagram representative of a system based on a processed requirements specification including a plurality of processed requirement statements and use cases. The design assistant tool may apply heuristic rules to the processed requirement statements and/or the processed use cases to determine various components of a functional design diagram. The design assistant tool may generate a technical design module based on the functional design diagram. The design assistant tool may allow various aspects of the functional design diagram to be modified to generate the technical design diagram.

Performance modeling of graphics processing unit application using static and dynamic analysis

Abstract: Graphics processing units (GPUs) have become an integral part of high‐performance computing to achieve an exascale performance. Understanding and estimating GPU performance is crucial for developers to design performance‐driven as well as energy‐efficient applications for a given architecture. This work presents a model developed using a static analysis of CUDA code to predict the execution time of NVIDIA GPU kernels without the need for running it. Here a PTX code is statically analyzed to extract instruction features, control flow, and data dependence. We propose a scheduling algorithm that satisfies resource reservation constraints to schedule these instructions in threads across streaming multiprocessors (SMs). We use dynamic analysis to build a set of memory access penalty models and use these models in conjunction with the scheduling information to estimate the execution time of the code. We present the experimental results which support that this approach works across architectures of NVIDIA GPUs. We first tested our model on two Kepler machines, where the mean percentage error (MPE)/mean absolute percentage error (MAPE) was − 8.88%/28.3% for Tesla K20 and − 5.66%/29.4% for Quadro K4200. We further tested the model on Maxwell and Pascal architectures and recorded the MPEs/MAPEs to be − 10.64%/47.8% and −3.94 %/28.5%, respectively.

Using Multivariate Statistics

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Pattern Recognition and Machine Learning

Abstract: Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Handbook of software reliability engineering

Abstract: Technical foundations introduction software reliability and system reliability the operational profile software reliability modelling survey model evaluation and recalibration techniques practices and experiences best current practice of SRE software reliability measurement experience measurement-based analysis of software reliability software fault and failure classification techniques trend analysis in validation and maintenance software reliability and field data analysis software reliability process assessment emerging techniques software reliability prediction metrics software reliability and testing fault-tolerant SRE software reliability using fault trees software reliability process simulation neural networks and software reliability. Appendices: software reliability tools software failure data set repository.