Sarojini Mandal

Bio: Sarojini Mandal is an academic researcher from University of Calcutta. The author has contributed to research in topics: Computational logic & Logic gate. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

Design of Memristor – CMOS based logic gates and logic circuits

Abstract: Recent researches are mostly focused on technology scaling as well as device size minimization design techniques following Moore’s law. Conventional computing architectures are unable to fulfill modern application demands. Memristor is a promising alternative device which has been developed by many researchers [2] to draw attention of its structure for numerous applications which includes computational logic, memory implementations and neuromorphic systems. This paper emphasizes the basic properties of memristor at the device level. Different digital circuits have been designed for logic operations and DSP applications. Design methodologies are developed for proper circuit design, and circuit parameters are taken from a very detailed device model and optimization techniques. The transient response of Hybrid CMOS-memristor based logic gates and different adder circuits (i.e, half adder, full adder, carry-save adder) and multiplier circuit are performed in Cadence 180nm technology.

Memristive Circuit Implementation of a Self-Repairing Network Based on Biological Astrocytes in Robot Application

Abstract: A large number of studies have shown that astrocytes can be combined with the presynaptic terminals and postsynaptic spines of neurons to constitute a triple synapse via an endocannabinoid retrograde messenger to achieve a self-repair ability in the human brain. Inspired by the biological self-repair mechanism of astrocytes, this work proposes a self-repairing neuron network circuit that utilizes a memristor to simulate changes in neurotransmitters when a set threshold is reached. The proposed circuit simulates an astrocyte-neuron network and comprises the following: 1) a single-astrocyte-neuron circuit module; 2) an astrocyte-neuron network circuit; 3) a module to detect malfunctions; and 4) a neuron PR (release probability of synaptic transmission) enhancement module. When faults occur in a synapse, the neuron module becomes silent or near silent because of the low PR of the synapses. The circuit can detect faults automatically. The damaged neuron can be repaired by enhancing the PR of other healthy neurons, analogous to the biological repair mechanism of astrocytes. This mechanism helps to repair the damaged circuit. A simulation of the circuit revealed the following: 1) as the number of neurons in the circuit increases, the self-repair ability strengthens and 2) as the number of damaged neurons in the astrocyte-neuron network increases, the self-repair ability weakens, and there is a significant degradation in the performance of the circuit. The self-repairing circuit was used for a robot, and it effectively improved the robots' performance and reliability.

Design of Memristor Based Logic Gates for Low Power Wireless Sensors in Biomedical Applications

Abstract: Current biomedical applications are using numerous wired and wireless sensors that keep track of various biological signals. These signals are continuously tracked, processed, and monitored for different biomedical applications. In this process, power consumption of the sensor is one of the important parameters to investigate. Most of the signal processing mechanisms is performed in mobile or computer-based applications. But data conversion and transfer can only be performed in sensor hardware where basic arithmetic operations are evaluated on voltages or current values. This work make use of a new and simple method to perform analog arithmetic operations, in which signals are interpreted and also stored using the memristor, rather than voltage or current. A new circuit is also being developed for programming the memristor's memristance with a predetermined analog value. The power dissipated by CMOS EX-NOR gate is highest, the power dissipated by memristor NOR gate is least. This paper will use the LTspice simulator, a common version of SPICE, to address memristor behavior.

Hybrid memristor-CMOS implementation of logic gates design using LTSpice

Abstract: In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.

Multifunctional Module Design Based on Hybrid CMOS-Memristor Logic Circuit

Abstract: With the rapid development of computer technology, logical circuits play an important role in many fields. Semiconductor transistors, as the basic logic circuit unit of modern computer hardware structure, also encounter more and more technical limitations in the highly integrated field such as computer chips. In order to continue Moore's Law effectively, higher requirements need to be put forward for the basic logic unit. The emergence of memristor opens up a new way to explore advanced computing architecture. This paper presents a MRL- based logic circuit in which input and output logic is provided by high and low voltage. Logic gate circuit elements such as XOR, NAND, NOR are implemented in conjunction with CMOS inverters. Through the construction of basic ratio logic gate, the adder and multiplier is simplified, and the result of signal simulation using LTspice software is completely correct. Finally, a multifunctional logic module is innovatively designed.