Sarosij Adak

Bio: Sarosij Adak is an academic researcher from Indian Institute of Engineering Science and Technology, Shibpur. The author has contributed to research in topics: MOSFET & High-electron-mobility transistor. The author has an hindex of 7, co-authored 24 publications receiving 132 citations. Previous affiliations of Sarosij Adak include Jadavpur University & VLSI Technology.

Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage

Abstract: In the present paper, we propose a novel device structure by introducing a source field-plated AlGaN/GaN in the metal oxide Semiconductor high electron mobility transistors (MOS-HEMT) structure having a relatively short gate length and short gate-to-drain distances. The 2D breakdown analysis is performed using Sentaurus TCAD simulator. The effects of gate to drain distance ( L g d ), source field plate length ( L f p ) and passivation layer thickness ( t p ) on breakdown voltage (BV) is analyzed. The simulations are done using the drift–diffusion (DD) model, which is calibrated/validated with the previously published experimental results. The breakdown voltage is observed to increase with increase in L f p and t p . Very high breakdown voltage of 752.8 V is obtained by optimizing the L f p to 3 µm and t p to 200 nm at a fixed gate to drain distance of 3.4 µm. The results show a great potential application of the ultra-thin HfAlO source field plated AlGaN/GaN MOS-HEMT to deliver high currents and power densities in high power microwave technologies.

Analysis of AlGaN/GaN HEMT using discrete field plate technique for high power and high frequency applications

Abstract: In this paper, the RF and DC characteristics of AlGaN/GaN High electron mobility transistor is analysed using discrete field plate technique. Surprisingly, it reduces the device parasitic capacitance exhibiting very low CGS and CGD of 5.8 × 10−13 F/mm and 4.2 × 10−13 F/mm respectively to improve the cut off frequency (fT) from 17.5 GHz to 20 GHz. The discrete field plate suppresses the maximum electric field between gate and drain region to achieve the high breakdown voltage of 330 V. The maximum transconductance (gm) achieved is 275 mS/mm, ensuring the better DC operation of the device. The simulated results clearly show that, the discrete field plate HEMTs are superior in performance over conventional GaN FP-HEMTs for future high frequency and high power applications.

Beyond Thermal Management: Incorporating p-Diamond Back-Barriers and Cap Layers Into AlGaN/GaN HEMTs

Abstract: This work explores the use of p-diamond back-barriers (BBs) and cap layers to enhance the performance of GaN-based high electron mobility transistors (HEMTs). Diamond can offer a heavily doped p-type layer, which is complementary to GaN electronics. Self-consistent electrothermal simulations reveal that the use of p-diamond BBs and cap layers can increase the breakdown voltage of GaN-based HEMTs by fourfold, at the same time that they enhance the 2-D-electron-gas confinement and reduce short channel effects. These results highlight that p-diamond layers can improve the performance of GaN HEMTs for high-power and high-frequency applications beyond the thermal improvements pursued until now.

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

Abstract: The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.