Satish S. Narkhede

Bio: Satish S. Narkhede is an academic researcher from Pune Institute of Computer Technology. The author has contributed to research in topics: Logic gate & AND-OR-Invert. The author has an hindex of 4, co-authored 11 publications receiving 35 citations. Previous affiliations of Satish S. Narkhede include Techno India & Massachusetts Institute of Technology.

Implementation of ternary logic gates using FGMOS

Abstract: Inthis paper we present the ternary logic gates implementation using FGMOS (Floating gate MOSFET) also calledMIFG MOSFET (Multi input floating gate MOSFET). Implementation using ternary logic have advantage than binary logic implementation in terms of more information capability, reduced interconnections and reduction in chip area. MIFG MOSFETs design reduces transistor count as a result area of chip will reduce. Ternary logic gates using MIFG MOSFETs reduces transistor count compared with CMOS design and CNTFET based designs.

Design of ternary D latch using carbon nanotube field effect transistors

Abstract: This paper presents a novel design of ternary D-latch using carbon nanotube field effect transistors. Ternary logic is a promising alternative to the conventional binary logic design technique, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to the reduced circuit overhead such as interconnects and chip area. In this paper novel design of D-latch for ternary logic based on CNTFET, using only basic gates STI, NTI, NOR, NAND and transmission gate, is proposed.

High performance implementation of mixing of column and inv mixing of column for AES on FPGA

Abstract: With the scenario of today, everybody using internet, net banking, and online shopping. Nowadays people having smart phone, palm top with latest updated operating system like windows 10, android. These gadgets are using as G.P.S., pocket banking, gaming, notepad, reminder and lot of ways. The most and very important thing is security. To fulfill this important requirement the efficient way is Encryption Decryption algorithm. But another point is speed means algorithm which would be efficient and fast. In order to achieve this requirement, different algorithms have been designed and implemented in the past, but every algorithm possess their own shortcomings with respect to an ASIC or an FPGA implementation. In this paper, I proposed and implemented of a one very useful method for area efficient and high performance for AES by using “Mixing of column and Inverse mixing of column operation” which is the one of the major block of operation in AES to implement the high performance of AES. I SIMULATE and SYNTHESIS on XILINX ISE 14.7 and implemented on VIRTEX 4. It is 100% area efficient; I compared my result with other. With this implementation I given the different methods for s-box and another methods to implement the mixing of column and inverse mixing of column.

Microstrip patch antenna array for Rainfall RADAR

Abstract: The design of a high Gain microstrip patch antenna array using microstrip line feed is presented in this paper. The design has been done for C band application at 5.81GHz for Rainfall RADAR also called as Precipitation Occurrence Sensor System (POSS). Array consisting of 16 elements of 4×4 were designed and simulated using HFSS v13 on Taconic TLY substrate of dielectric constant 2.2 and height of substrate equal to 1.58 mm. For the proposed antenna, the achieved gain is 19.5 dBi, return loss is ≤ 30 dB, 3 dB bandwidth of 170 MHz with low side lobes and back lobe. The Array antenna was excited by uniform amplitude and phase feeding method. A comparative analysis was done between 1×2, 2×2 and 4×4 array. It was found that gain increases at cost of bandwidth.

VLSI implementation of ternary gates using Tanner Tool

Abstract: A new era of digital computation investigates the advantages of non-binary machine logic over the conventional binary logic. Multi Valued Logic [MVL] systems, where the radix is greater than 2 are evolving as a thrust area of research. Ternary logic has gained wide popularity and offers several potential opportunities for the improvement of present VLSI circuit designs. Ternary gates form the fundamental element for numerous ternary circuits, making its efficient design and simulation indispensable. This paper presents the implementation and simulation of ternary gates (TNOT, TNAND, TNOR) using injected voltage method. The binary CMOS logic is exploited to achieve the ternary logic values. The performance analysis of the ternary gates in terms of rise time, fall time and power dissipation is examined using Tanner Tool, version 13.02. The prominent subsets (S-Edit, L-Edit, T-Spice and W-Edit) of the tanner tool are used to derive the various device parameters and further verify the functionality of the gates. The layouts of the designed gates are also presented.

Advanced Encryption Standard (AES).

Abstract: Im Jahre 1977 wurde der „Data Encryption Algorithm“ (DEA) vom „National Bureau of Standards“ (NBS, später „National Institute of Standards and Technology“ – NIST) zum amerikanischen Verschlüsselungsstandard für Bundesbehörden erklärt [NBS_77]. 1981 folgte die Verabschiedung der DEA-Spezifikation als ANSI-Standard „DES“ [ANSI_81]. Die Empfehlung des DES als StandardVerschlüsselungsverfahren wurde auf fünf Jahre befristet und 1983, 1988 und 1993 um jeweils weitere fünf Jahre verlängert. Derzeit liegt eine Neufassung des NISTStandards vor [NIST_99], in dem der DES für weitere fünf Jahre übergangsweise zugelassen sein soll, aber die Verwendung von Triple-DES empfohlen wird: eine dreifache Anwendung des DES mit drei verschiedenen Schlüsseln (effektive Schlüssellänge: 168 bit) [NIST_99]. Der DES basiert auf einer von Horst Feistel bei IBM entwickelten Blockchiffre („Lucipher“) mit einer Schlüssellänge von 128 bit. Da die amerikanische „National Security Agency“ (NSA) dafür gesorgt hatte, daß der DES eine Schlüssellänge von lediglich 64 bit besitzt, von denen nur 56 bit relevant sind, und spezielle Substitutionsboxen (den „kryptographischen Kern“ des Verfahrens) erhielt, deren Konstruktionskriterien von der NSA nicht veröffentlicht wurden, war das Verfahren von Beginn an umstritten. Kritiker nahmen an, daß es eine geheime „Trapdoor“ in dem Verfahren gäbe, die der NSA eine OnlineEntschlüsselung auch ohne Kenntnis des Schlüssels erlauben würde. Zwar ließ sich dieser Verdacht nicht erhärten, aber sowohl die Zunahme von Rechenleistung als auch die Parallelisierung von Suchalgorithmen machen heute eine Schlüssellänge von 56 bit zum Sicherheitsrisiko. Zuletzt konnte 1998 mit einer von der „Electronic Frontier Foundation“ (EFF) entwickelten Spezialmaschine mit 1.800 parallel arbeitenden, eigens entwickelten Krypto-Prozessoren ein DES-Schlüssel in einer Rekordzeit von 2,5 Tagen gefunden werden. Um einen Nachfolger für den DES zu finden, kündigte das NIST am 2. Januar 1997 die Suche nach einem „Advanced Encryption Standard“ (AES) an. Ziel dieser Initiative ist, in enger Kooperation mit Forschung und Industrie ein symmetrisches Verschlüsselungsverfahren zu finden, das geeignet ist, bis weit ins 21. Jahrhundert hinein amerikanische Behördendaten wirkungsvoll zu verschlüsseln. Dazu wurde am 12. September 1997 ein offizieller „Call for Algorithm“ ausgeschrieben. An die vorzuschlagenden symmetrischen Verschlüsselungsalgorithmen wurden die folgenden Anforderungen gestellt: nicht-klassifiziert und veröffentlicht, weltweit lizenzfrei verfügbar, effizient implementierbar in Hardund Software, Blockchiffren mit einer Blocklänge von 128 bit sowie Schlüssellängen von 128, 192 und 256 bit unterstützt. Auf der ersten „AES Candidate Conference“ (AES1) veröffentlichte das NIST am 20. August 1998 eine Liste von 15 vorgeschlagenen Algorithmen und forderte die Fachöffentlichkeit zu deren Analyse auf. Die Ergebnisse wurden auf der zweiten „AES Candidate Conference“ (22.-23. März 1999 in Rom, AES2) vorgestellt und unter internationalen Kryptologen diskutiert. Die Kommentierungsphase endete am 15. April 1999. Auf der Basis der eingegangenen Kommentare und Analysen wählte das NIST fünf Kandidaten aus, die es am 9. August 1999 öffentlich bekanntmachte: MARS (IBM) RC6 (RSA Lab.) Rijndael (Daemen, Rijmen) Serpent (Anderson, Biham, Knudsen) Twofish (Schneier, Kelsey, Whiting, Wagner, Hall, Ferguson).

High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits

Abstract: Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary NAND (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (V dd and V dd /2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively.

Lightweight Cryptography for Internet of Insecure Things: A Survey

Abstract: This paper surveys Lightweight Cryptographic solutions for Internet of Things (IoT). This survey covers comprehensively a flow of security measures from Lightweight Cryptographic solutions to comparison among different types of block ciphers. It also includes comparison between Hardware vs Software solutions and different recent approaches of the most trusted and researched block cipher, Advanced Encryption Standard (AES) in terms of architecture, Mix-Column/S-box modify strategy and attacks for IoT security. According to the study, lightweight AES has proved to be a good security solution for constrained IoT devices.

Memristor based unbalanced ternary logic gates

Abstract: This paper introduces a novel design of basic ternary logic gates using memristor, which is a set of AND, OR, inverters, NOR, and NAND gates. The ternary logic is a promising alternative to the conventional binary logic design technique. The resistive-load MOSFET-based ternary logic gates have already been proposed. The proposed memristor-based circuit replaces the large resistors by employing active load memristor in the ternary logic gates. The proposed ternary logic circuits are shown to have great significant advantages relative to other known binary circuits and ternary circuits like low power dissipation, chip area, component count, dense fabrication and cost. The paper concludes with an implementation of the ternary logic gates using SPICE simulations.