S
Satoshi Yamakawa
Researcher at Mitsubishi Electric
Publications - 57
Citations - 646
Satoshi Yamakawa is an academic researcher from Mitsubishi Electric. The author has contributed to research in topics: MOSFET & Schottky barrier. The author has an hindex of 11, co-authored 56 publications receiving 511 citations.
Papers
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Journal ArticleDOI
4H-SiC Trench MOSFET with Bottom Oxide Protection
Yasuhiro Kagawa,Nobuo Fujiwara,Katsutoshi Sugawara,Rina Tanaka,Fukui Yutaka,Yasuki Yamamoto,Naruhisa Miura,Masayuki Imaizumi,Shuhei Nakata,Satoshi Yamakawa +9 more
TL;DR: In this article, a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection was developed.
Proceedings ArticleDOI
6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module
Koutarou Kawahara,Shiro Hino,Koji Sadamatsu,Yukiyasu Nakao,Yamashiro Yusuke,Yasuki Yamamoto,T. Iwamatsu,Shuhei Nakata,Shingo Tomohisa,Satoshi Yamakawa +9 more
TL;DR: In this article, an SBD is embedded into each unit cell of a 6.5 kV SiC-MOSFET to suppress current conduction of the body diodes, which causes bipolar degradation following the expansion of stacking faults.
Journal ArticleDOI
Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress
Kazuya Konishi,Shigehisa Yamamoto,Shuhei Nakata,Yu Nakamura,Yosuke Nakanishi,Takanori Tanaka,Yoichiro Mitani,Nobuyuki Tomita,Yoshihiko Toyoda,Satoshi Yamakawa +9 more
TL;DR: In this paper, the authors evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocation (TEDs) under the current stress to the pn devices and analyze the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques.
Journal ArticleDOI
Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode
Shiro Hino,Hatta Hideyuki,Koji Sadamatsu,Y. Nagahisa,Shigehisa Yamamoto,T. Iwamatsu,Yasuki Yamamoto,Masayuki Imaizumi,Shuhei Nakata,Satoshi Yamakawa +9 more
TL;DR: In this paper, an external Schottky barrier diodes (SBD) is used to suppress the conduction of the body diode of an MOSFET, which can reduce the total chip size of high voltage modules.
Journal ArticleDOI
3.3 kV/1500 A power modules for the world’s first all-SiC traction inverter
Kenji Hamada,Shiro Hino,Naruhisa Miura,Hiroshi Watanabe,Shuhei Nakata,Eisuke Suekawa,Yuji Ebiike,Masayuki Imaizumi,Isao Umezaki,Satoshi Yamakawa +9 more
TL;DR: In this article, the authors have successfully developed 4H-SiC devices including metaloxide-semiconductor field effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) with a rated voltage of 3.3 kV.