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Author

Satou Shiyuuichi

Bio: Satou Shiyuuichi is an academic researcher. The author has contributed to research in topics: Field-effect transistor. The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Papers
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Patent
24 Aug 1977
TL;DR: In this article, the authors proposed a method to obtain transconductances higher than MIS-FETs wherein remote cut-off characteristics are obtained by controlling only the channel current flowing the surface of a semiconductor.
Abstract: PURPOSE:Transconductances higher than MIS-FETs wherein remote cut-off characteristics are obtained by controlling only the channel current flowing the surface of a semiconductor are obtained and a MIS-FET having remote cut-off characteristics wherein the variation in the charactiristics owing to temperature change is less and noise is reduced is obtained

4 citations


Cited by
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Patent
16 Nov 1982
TL;DR: In this paper, the authors proposed to enhance the withstand voltage of an FET by disposing the channel region in the vicinity of the terminal at the drain side of the first gate electrode and an impurity layer under a field isolating oxidized film so as not to contact each other.
Abstract: PURPOSE:To enhance the withstand voltage of an FET and to enable to operate at a high voltage in an FET having 2-layer gate structure by disposing the channel region in the vicinity of the terminal at the drain side of the first gate electrode and an impurity layer under a field isolating oxidized film so as not to contact each other. CONSTITUTION:A thick field isolating oxidized film 36 is formed with a P type impurity layer 62 laid as a primary layer at the periphery of a P type Si substrate 30, and an N type drain region 33 and an annular N type source region 32 which surrounds the region 33 are respectively diffused and formed in the substrate 30 surrounded by the film 36. Then, the first annular gate 31 is formed between the regions 33 and 32, the second annular gate 37 is similarly formed on the first gate, and a connecting conductor 38 is mounted on one end of the second gate. After thus constructed, the region 33 and the gate 37 are connected to a drain electrode. In other words, the channel region in the vicinity of the end of the first gate 31 of the drain side and the layer 62 under the film 36 are isolated in the structure, thereby preventing the withstanding voltage from decreasing.

5 citations

Patent
05 Feb 1980
TL;DR: In this paper, a pseudo-channel area with the same N type impurity as source area S and drain area D is formed between the said areas with a channel area CH left on insulation layer I and connected to the counter side to the insulation Layer I.
Abstract: PURPOSE:To minimize consumption power by arranging a pseudo-channel area in parallel with a channel area extending between source area and drain area. CONSTITUTION:A pseudo-channel area CH' having the same N type as source area S and drain area D is formed between the said areas with a channel area CH left on insulation layer I and connected thereto on counter side to the insulation layer I. In this case, the channel area CH and the pseudo-channel area CH' comprise introducing N type impurity into a substrate 1 through its main side and then introducing P type impurity into the substrate 1 through its main side.

3 citations

Patent
29 Nov 1984
TL;DR: In this paper, the authors proposed to lower the parasitic resistance of a gate and increase a switching rate by forming a channel diffusion region of a shape that a low resistor is connected in parallel with a band-shaped gate diffusion region.
Abstract: PURPOSE:To lower the parasitic resistance of a gate, and to increase a switching rate by forming a channel diffusion region of a shape that a low resistor is connected in parallel with a band-shaped gate diffusion region. CONSTITUTION:A pair of a band-shaped P type source diffusion region 15 and a band-shaped P type diffusion region arranged in parallel at a regular interval D1 are formed to the surface of an N type Si epitaxial layer 14. A plural row of P type channel diffusion regions 17 are formed to the surface of the layer 14 between these region 15 and region 16 so as to contain the region 15 and the region 16. A band-shaped gate diffusion region 18, which runs parallel with the region 15 and the region 16 and is shallower than the regions 17, is shaped at the position of equal distances from the region 15 and the region 16. According to such constitution, since a low resistor consisting of the layer 14 and an N type buried diffusion layer 12 in the lower section of the layer 14 is connected in parallel with the region 18, the parasitic resistance of a gate is reduced largely, and the switching rate of the titled junction type FET is increased.

1 citations

Patent
31 Jul 2007
TL;DR: In this paper, a brush for a coating gun which is capable of being attached detachably to the coating gun capable of spraying a coating material to diffuse to form an elliptical-shaped cross-section while keeping coating performance was presented.
Abstract: PROBLEM TO BE SOLVED: To provide a brush for a coating gun which is capable of being attached detachably to the coating gun capable of spraying a coating material to diffuse to form an elliptical-shaped cross-section while keeping coating performance by applying the coating material on a surface to be coated with the brush and coating not only a narrow part but a wide part of the surface to be coated with excellent workability by forming the shape of the brush into the elliptical shape in the cross section to follow the diffusion of the elliptical shape of the coating material. SOLUTION: The brush for the coating gun is attached detachably directly or indirectly to a spray port part 3b of the coating gun 3 for spraying the misty coating material by the operation of a trigger 3a. The brush 1 for the coating gun has an annular cross-sectional elliptical shape having a prescribed thickness and the opening cross-sectional area increases from the spray opening part toward the tip. COPYRIGHT: (C)2009,JPO&INPIT