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Satyabrata Jit

Researcher at Indian Institute of Technology (BHU) Varanasi

Publications -  281
Citations -  3565

Satyabrata Jit is an academic researcher from Indian Institute of Technology (BHU) Varanasi. The author has contributed to research in topics: Threshold voltage & MOSFET. The author has an hindex of 26, co-authored 259 publications receiving 2510 citations. Previous affiliations of Satyabrata Jit include Georgia State University & Banaras Hindu University.

Papers
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2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

Sanjay Kumar, +6 more
- 07 Feb 2017 - 
TL;DR: In this paper, a physics-based 2D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs with SiO2/HfO2 stacked gate-oxide structure has been developed.
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A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO 2 /High- $k$ Stacked Gate-Oxide Structure

Sanjay Kumar, +5 more
- 07 Jun 2016 - 
TL;DR: In this article, a 2D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FETs with a SiO2/High- ${k}$ stacked gate-oxide structure is proposed.
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Coverage and Connectivity in WSNs: A Survey, Research Issues and Challenges

Abhishek Tripathi, +5 more
- 05 Jun 2018 - 
TL;DR: This paper surveys the existing work done to address various issues and challenges for solving the coverage and connectivity problems in WSNs and reviews a brief but complete overview of the various solutions of coverage problems in connected W SNs.
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2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs

Ekta Goel, +5 more
- 04 Feb 2016 - 
TL;DR: In this article, a 2D analytical model for the surface potential and threshold voltage of graded-channel dual-material double-gate (GCDMDG) MOSFETs obtained by intermixing the concepts of graded doping in channel and dual material in gate engineering has been proposed.
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Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications

Manas Ranjan Tripathy, +6 more
- 05 Feb 2020 - 
TL;DR: In this article, the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket was investigated for the first time to enhance the carrier tunneling through the source-channel (Si) heterojunction.