S
Saurabh N. Adya
Researcher at Intel
Publications - 23
Citations - 1408
Saurabh N. Adya is an academic researcher from Intel. The author has contributed to research in topics: Floorplan & Placement. The author has an hindex of 13, co-authored 23 publications receiving 1358 citations. Previous affiliations of Saurabh N. Adya include Synopsys & University of Michigan.
Papers
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Journal ArticleDOI
Fixed-outline floorplanning: enabling hierarchical design
Saurabh N. Adya,Igor L. Markov +1 more
TL;DR: This paper studies the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs and proposes new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context.
Proceedings ArticleDOI
Unification of partitioning, placement and floorplanning
TL;DR: This work proposes to integrate min-cut placement with fixed-outline floor-planning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving routability, and proposes that free-shape rectilinear floor plannerning can be used with rough module-area estimates before synthesis.
Proceedings ArticleDOI
Capo: robust and scalable open-source min-cut floorplacer
Jarrod A. Roy,David A. Papa,Saurabh N. Adya,Hayward H. Chan,Ng Aaron,James F. Lu,Igor L. Markov +6 more
TL;DR: The overall structure of Capo is surveyed, recent improvements are discussed and ongoing research is described, which describes recent improvements and describes ongoing research.
Journal ArticleDOI
Min-cut floorplacement
TL;DR: The authors propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement,floorplanning, mixed-size placement, and achieving routability.
Proceedings ArticleDOI
Fixed-outline floorplanning through better local search
Saurabh N. Adya,Igor L. Markov +1 more
TL;DR: The fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs is studied and new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context are suggested.