S
Saurabh Saxena
Researcher at Indian Institute of Technology Madras
Publications - 40
Citations - 607
Saurabh Saxena is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Phase-locked loop & Jitter. The author has an hindex of 13, co-authored 34 publications receiving 496 citations. Previous affiliations of Saurabh Saxena include University of Illinois at Urbana–Champaign & Oregon State University.
Papers
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Journal ArticleDOI
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
Guanghua Shu,Woo-Seok Choi,Saurabh Saxena,Mrunmay Talegaonkar,Tejasvi Anand,Ahmed Elkholy,Amr Elshazly,Pavan Kumar Hanumolu +7 more
TL;DR: A ring-oscillator-based two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs.
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A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
TL;DR: This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization Noise.
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A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
Romesh Kumar Nandwana,Tejasvi Anand,Saurabh Saxena,Seong Joong Kim,Mrunmay Talegaonkar,Ahmed Elkholy,Woo-Seok Choi,Amr Elshazly,Pavan Kumar Hanumolu +8 more
TL;DR: A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs and alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression.
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A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop
Guanghua Shu,Saurabh Saxena,Woo-Seok Choi,Mrunmay Talegaonkar,Rajesh Inti,Amr Elshazly,Brian Young,Pavan Kumar Hanumolu +7 more
TL;DR: By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain.
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A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power
TL;DR: A new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area is presented and other changes are introduced to improve the modulators dynamic range (DR) and power dissipation.